One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
DAC312–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Resolution
Monotonicity
Differential Nonlinearity
Nonlinearity
Full-Scale Current
Full-Scale Tempco
Symbol
Conditions
(@ V
S
= 15 V, I
REF
= 1.0 mA, 0 C
≤
T
A
≤
+70 C for DAC312E and –40 C
≤
T
A
≤
+85 C
for DAC312F, DAC312H, unless otherwise noted. Output characteristics refer
to both I
OUT
and I
OUT
.)
Min
12
12
DAC312E
Typ
Max
Min
12
12
±
0.0125
±
0.5
±
0.05
±
0.0250
±
1
±
0.05
DAC312F
Typ
Max
Min
12
12
DAC312H
Typ
Max
Units
DNL
INL
I
FS
TCI
FS
Deviation from Ideal
Step Size
2
Deviation from Ideal
Straight Line
1
V
REF
= 10 V
R
14
= R
15
= 10 kΩ
2
Bits
Bits
±
0.0250 %FS
±
1
LSB
±
0.05
%FS
3.967
3.999
±
5
±
0.005
4.031
±
20
±
0.002
3.935 3.999
±
10
±
0.001
4.063
±
40
±
0.004
3.935 3.999
±
80
±
0.008
4.063
mA
ppm/°C
%FS/°C
Output Voltage Compliance
Full-Scale Symmetry
Zero-Scale Current
Settling Time
Propagation Delay–All Bits
V
OC
I
FSS
I
ZS
t
S
t
PLH
t
PHL
R
O
C
OUT
V
IL
V
IH
I
IN
V
IS
I
15
dl/dt
PSSI
FS+
PSSI
FS–
DNL Specification Guaran-
teed over Compliance Range
|I
FS
|–|I
FS
|
To
±
1/2 LSB, All Bits
Switched ON or OFF
1
All Bits Switched 50% Point
Logic Swing to 50% Point
Output
1
–5
±
0.4
+10
±
1
0.10
500
50
50
–5
±
0.4
+10
±
2
0.10
500
50
50
–5
±
0.4
+10
±
2
0.10
500
50
50
V
µA
µA
ns
ns
ns
MΩ
pF
250
25
25
>10
20
250
25
25
>10
20
250
25
25
>10
20
Output Resistance
Output Capacitance
Logic Input
Levels “0”
Levels “1”
Logic Input Current
Logic Input Swing
Reference Bias Current
Reference Input
Slew Rate
Power Supply Sensitivity
V
LC
= GND
V
LC
= GND
V
IN
= –5 to +18 V
0.8
2
–5
0
40
+18
–2
2
–5
0
4
±
0.001
0.8
2
40
+18
–2
–5
0
4
±
0.001
0.8
40
+18
–2
–0.5
8
±
0.0005
–0.5
8
±
0.0005
–0.5
8
±
0.0005
V
V
µA
V
µA
mA/µs
Power Supply Range
Power Supply Current
Power Dissipation
V+
V–
I+
I–
I+
I–
P
d
R
14(eq)
= 800
Ω,
C
C
= 0 pF
1
V+ = +13.5 V to +16.5 V,
V– = –15 V
V– = –13.5 V to –16.5 V,
V+ = +15 V
V
OUT
= 0 V
V
OUT
= 0 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
4
±
0.001
%FS/%∆V
%FS/%∆V
V
V
mA
mA
mA
mA
mW
mW
4.5
–18
±
0.00025
±
0.001
18
–10.8
3.3
7
–13.9
–18
3.9
7
–13.9
–18
225
305
267
375
4.5
–18
±
0.00025
±
0.001
18
–10.8
3.3
7
–13.9
–18
3.9
7
–13.9
–18
225
305
267
375
4.5
–18
±
0.00025
±
0.001
18
–10.8
3.3
7
–13 9
–18
3.9
7
–13.9
–18
225
305
267
375
TYPICAL ELECTRICAL CHARACTERISTICS
characteristics refer to both I
OUT
and I
OUT
.
Parameter
Reference Input
Slew Rate
Propagation Delay
Settling Time
Symbol
dl/dt
t
PLH
, t
PHL
t
S
Any Bit
To
±
1/2 LSB, All
Bits Switched ON
or OFF.
Conditions
@ 25 C; V
S
=
15 V, and I
REF
= 1.0 mA, unless otherwise noted. Output
DAC312N
Typical
8
25
250
±
10
DAC312G
Typical
8
25
250
±
10
Units
mA/µs
ns
ns
ppm/°C
Full-Scale
TC
IFS
–2–
REV. C
DAC312
ELECTRICAL CHARACTERISTICS
Parameter
Logic Input
Levels “0”
Logic Input
Levels “1”
Logic Input
Current
Logic Input
Swing
Reference Bias
Current
Reference Input
Slew Rate
Power Supply
Sensitivity
Power Supply
Range
Power Supply
Current
Power
Dissipation
Symbol
Conditions
@ V
S
= 15 V, I
REF
= 1.0 mA, 0 C
≤
T
A
≤
70 C for DAC312E and –40 C
≤
T
A
≤
+85 C for
DAC312F, DAC312H, unless otherwise noted. Output characteristics refer to both I
OUT
and I
OUT
.
Continued
Min
DAC312E
Typ
Max
DAC312F
Min Typ
Max
DAC312H
Min Typ
Max
Units
V
IL
V
IH
I
IN
V
IS
I
15
dl/dt
V
LC
= GND
V
LC
= GND
V
IN
= –5 V to +18 V
–5
0
R
14(eq)
= 800
Ω
C
C
= 0 pF (Note 1)
V+ = +13.5 V to +16.5 V,
V– = –15 V
V– = –13.5 V to –16.5 V,
V+ = +15 V
V
OUT
= 0 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
4.5
–18
3.3
–13.9
3.9
–13.9
225
267
4
–0.5
8
2
0.8
2
40
+18
–2
–5
0
4
–0.5
8
0.8
2
40
+18
–2
–5
0
4
–0.5
8
0.8
V
V
40
+18
–2
µA
V
µA
mA/µs
±
0.0005
±
0.001
±
0.00025
±
0.001
18
–10.8
7
–18
7
–18
305
375
4.5
–18
±
0.0005
±
0.001
±
0.00025
±
0.001
18
–10.8
3.3
–13.9
3.9
–13.9
225
267
7
–18
7
–18
305
375
4.5
–18
±
0.0005
±
0.001 %FS/%∆V
±
0.00025
±
0.001 %FS/%∆V
18
–10.8
3.3
–13.9
3.9
–13.9
225
267
7
–18
7
–18
305
375
PSSI
FS+
PSSI
FS–
V+
V–
I+
I–
I+
I–
P
d
V
mA
mW
NOTES
1
Guaranteed by design.
2
T
A
= +25°C for DAC312H grade only.
Specifications subject to change without notice.
REV. C
–3–
DAC312
WAFER TEST LIMITS
@ V =
S
15 V, I
REF
= 1.0 mA, T
A
= 25 C, unless otherwise noted. Output characteristics refer to both I
OUT
and I
OUT
.
Conditions
DAC312N
Limit
12
12
±
0.05
Full-Scale Current
Change <1/2 LSB
V
REF
= 10.000 V
R
14
, R
15
= 10.000 kΩ
+10
–5
4.031
3.967
±
1
0.1
Deviation from
Ideal Step Size
V
LC
= GND
V
LC
= GND
±
0.012
±
1/2
0.8
2
+18
–5
–2
V+ = +13.5 V to +16.5 V, V– = –15 V
V– = –13.5 V to –16.5 V, V+ = +15 V
V
S
= +15 V
I
REF
≤
1.0 mA
V
S
= +15 V
I
REF
≤
1.0 mA
±
0.001
±
0.001
7
–18
375
DAC312G
Limit
12
12
±
0.05
+10
–5
4.063
3.935
±
2
0.1
±
0.025
±
1
0.8
2
+18
–5
–2
±
0.001
±
0.001
7
–18
375
Units
Bits min
Bits min
%FS max
V max
V min
mA max
mA min
µA
max
µA
max
%FS max
Bits (LSB) max
V max
V min
V max
V min
µA
max
%/%max
mA max
mW max
Parameter
Resolution
Monotonicity
Nonlinearity
Output Voltage
Compliance
Full-Scale
Current
Full-Scale Symmetry
Zero-Scale Current
Differential
Nonlinearity
Logic Input Levels “0”
Logic Input Levels “1”
Logic Input Swing
Reference Bias
Current
Power Supply
Sensitivity
Power Supply
Current
Power
Dissipation
Symbol
Voc
I
FSS
I
ZS
DNL
V
IL
V
IH
V
IS
I
15
PSSI
FS+
PSSI
FS–
I+
I–
P
D
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
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Embedded System
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