Supports 100 MHz and 125 MHz reference clock frequencies
–
Flexible port clocking modes
•
Common clock
•
Non-common clock
•
Local port clock with SSC (spread spectrum setting) and port
reference clock input
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 34
2013 Integrated Device Technology, Inc
December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Hot-Plug and Hot Swap
–
Hot-plug controller on all ports
•
Hot-plug supported on all downstream switch ports
–
All ports support hot-plug using low-cost external I
2
C I/O
expanders
–
Configurable presence-detect supports card and cable appli-
cations
–
GPE output pin for hot-plug event notification
•
Enables SCI/SMI generation for legacy operating system
support
–
Hot-swap capable I/O
Power Management
–
Supports D0, D3hot and D3 power management states
–
Active State Power Management (ASPM)
•
Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
•
Configurable L0s and L1 entry timers allow performance/
power-savings tuning
–
SerDes power savings
•
Supports low swing / half-swing SerDes operation
•
SerDes associated with unused ports are turned off
•
SerDes associated with unused lanes are placed in a low
power state
Reliability, Availability, and Serviceability (RAS)
–
ECRC support
–
AER on all ports
–
SECDED ECC protection on all internal RAMs
–
End-to-end data path parity protection
–
Checksum Serial EEPROM content protected
–
Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Initialization / Configuration
–
Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
–
Common switch configurations are supported with pin strap-
ping (no external components)
–
Supports in-system Serial EEPROM initialization/program-
ming
On-Die Temperature Sensor
–
Range of 0 to 127.5 degrees Celsius
–
Three programmable temperature thresholds with over and
under temperature threshold alarms
–
Automatic recording of maximum high or minimum low
temperature
9 General Purpose I/O
Test and Debug
–
Ability to inject AER errors simplifies in system error handling
software validation
–
On-chip link activity and status outputs available for several
ports
–
Per port link activity and status outputs available using
external I
2
C I/O expander for all remaining ports
–
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Standards and Compatibility
–
PCI Express Base Specification 2.1 compliant
–
Implements the following optional PCI Express features
•
Advanced Error Reporting (AER) on all ports
•
End-to-End CRC (ECRC)
•
Access Control Services (ACS)
•
Device Serial Number Enhanced Capability
•
Sub-System ID and Sub-System Vendor ID Capability
•
Internal Error Reporting
•
Multicast
•
VGA and ISA enable
•
L0s and L1 ASPM
•
ARI
Power Supplies
–
Requires three power supply voltages (1.0V, 2.5V, and 3.3V)
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
Product Description
With Non-Transparent Bridging functionality and innovative Switch
Partitioning feature, the PES24NT6AG2 allows true multi-host or multi-
processor communications in a single device. Integrated DMA control-
lers enable high-performance system design by off-loading data transfer
operations across memories from the processors. Each lane is capable
of 5 GT/s link speed in both directions and is fully compliant with PCI
Express Base Specification 2.1.
A non-transparent bridge (NTB) is required when two PCI Express
domains need to communicate to each other. The main function of the
NTB block is to initialize and translate addresses and device IDs to
allow data exchange across PCI Express domains. The major function-
alities of the NTB block are summarized in
Table 1.
2 of 34
December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Block Diagram
6-Port Switch Core / 24 Gen2 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes SerDes
(Port 0)
(Port 2)
(Ports 4, 6, 8,)
(Port 12)
Figure 1 PES24NT6AG2 Block Diagram
Function
NTB ports
Mapping table
entries
Mapping windows
Number
Up to 6
Up to 64 for entire
device
Six 32-bits or three
64-bits
Description
Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots.
Each device can have up to 64 masters ID for address and ID translations.
Each NT port has six BARs, where each BAR opening an NT window to another domain.
Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment
has independent translation programming and is associated with an entry in a look-up table.
Doorbell register is used for event signaling between domains, where an outbound doorbell bit
sets a corresponding bit at the inbound doorbell in the other domain.
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain.
Table 1 Non-Transparent Bridge Function Summary
Address translation Direct-address and
lookup table trans-
lations
Doorbell registers
Message registers
32 bits
4 inbound and out-
bound registers of
32-bits
SMBus Interface
The PES24NT6AG2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES24NT6AG2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES24NT6AG2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface
is also used by an external Hot-Plug I/O expander.
3 of 34
December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
SSMBADDR2 pins. As shown in
Figure 2,
the master and slave SMBuses may only be used in a split configuration. In the split configuration, the
master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not
support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM
and I/O expander slaves.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 2 Split SMBus Interface Configuration
Hot-Plug Interface
The PES24NT6AG2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES24NT6AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES24NT6AG2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES24NT6AG2. In response to an I/O expander interrupt, the PES24NT6AG2 generates
an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24NT6AG2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus
slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES24NT6AG2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Note:
Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc.
4 of 34
December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Signal
PE00RN[3:0]
PE00RP[3:0]
PE00TN[3:0]
PE00TP[3:0]
PE02RN[3:0]
PE02RP[3:0]
PE02TN[3:0]
PE02TP[3:0]
PE04RN[3:0]
PE04RP[3:0]
PE04TN[3:0]
PE04TP[3:0]
PE06RN[3:0]
PE06RP[3:0]
PE06TN[3:0]
PE06TP[3:0]
PE08RN[3:0]
PE08RP[3:0]
PE08TN[3:0]
PE08TP[3:0]
PE12RN[3:0]
PE12RP[3:0]
PE12TN[3:0]
PE12TP[3:0]
Type
I
O
I
O
I
O
I
O
I
O
I
O
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive pairs for
port 0.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 0.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive pairs for
port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 2.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive pairs for
port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 4.
PCI Express Port 6 Serial Data Receive.
Differential PCI Express receive pairs for
port 6.
PCI Express Port 6 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 6.
PCI Express Port 8 Serial Data Receive.
Differential PCI Express receive pair for
port 8.
PCI Express Port 8 Serial Data Transmit.
Differential PCI Express transmit pair for
port 8.
PCI Express Port 12 Serial Data Receive.
Differential PCI Express receive pair for
port 12.
PCI Express Port 12 Serial Data Transmit.
Differential PCI Express transmit pair for
port 12.
Table 2 PCI Express Interface Pins
Signal
GCLKN[1:0]
GCLKP[1:0]
Type
I
Name/Description
Global Reference Clock.
Differential reference clock input pairs. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
Note: Both pairs of the Global Reference Clocks must be connected to and
derived from the same clock source. Refer to the Overview section of
Chapter 2 in the PES24NT6AG2 User Manual for additional details.
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