DDN50P467CTXLF datasheet, PDF - EEWORLD Datasheet

DDN50P467CTXLF: DescriptionD Subminiature Connector, 50 Contact(s), Male, Wire Wrap Terminal, LEAD FREE; CategoryThe connector The connector; File Size183KB，1 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/; Environmental Compliance

Download Datasheet Parametric View All

DDN50P467CTXLF Overview

D Subminiature Connector, 50 Contact(s), Male, Wire Wrap Terminal, LEAD FREE

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Amphenol
package instruction	LEAD FREE
Reach Compliance Code	compliant
Connector type	D SUBMINIATURE CONNECTOR
Contact to complete cooperation	GOLD (16) OVER NICKEL
Contact completed and terminated	MATTE TIN (79) OVER NICKEL
Contact point gender	MALE
Contact material	COPPER ALLOY
DIN compliance	NO
empty shell	NO
Filter function	NO
IEC compliance	NO
insulator material	POLYETHYLENE
JESD-609 code	e3
MIL compliance	NO
Manufacturer's serial number	D
Mixed contacts	NO
Installation type	BOARD
Options	GENERAL PURPOSE
Shell surface	ZINC
Shell material	STEEL
Housing size	5/D
Termination type	WIRE WRAP
Total number of contacts	50
UL Flammability Code	94V-0

C-DSUB-0065

PDM: Rev:D

STATUS:

Released

Printed: Sep 15, 2006

A Range Extension Reference Design Using the ADF7023 and RFFM6901 915 MHz ISM Band Transceiver Module: [i=s] This post was last edited by Yuzhong on 2014-11-12 08:41 [/i] [b]A range extension reference design using ADF7023 and RFFM6901 915 MHz ISM band transceiver module (with diversity switch) downloa...; 雨中 ADI Reference Circuit

The industry insider whistleblower Junzheng 4725 4755’s shocking revelations!: 1. In fact, the ECC error correction capability of Ingenic 4725 is only 4bit ECC, which means that the currently used 50nm Flash (8bit ECC error correction requirement) is not well supported, not to m...; KG5 Mobile and portable

What is the difference between build and compile?: In keil uv3, build target "target1" compile *.1c compile *.2c compile *.3c compile *.4c link… programsize… error warning… What is the difference between build and compile?...; fengyun11747 MCU

Verilog writing problem: Why is there no output for the newly added pin after the Verilog program is modified? Is it because of the configuration file?...; Maxwell_CZH FPGA/CPLD

FPGA Power Consumption: The project needs to complete the above functions, namely AD/DA, storage, transmission, control algorithm (control cycle 40us, the algorithm is slightly more complicated than PID, and requires single-...; sudongpo2018 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components