UNISONIC TECHNOLOGIES CO., LTD
M1008
Preliminary
CMOS IC
16-BIT CCD/CIS ANALOG
SIGNAL PROCESSOR
DESCRIPTION
The
M1008
is a 16-bit CCD/CIS analog signal processor for
imaging applications. A 3-channel architecture is designed to sample
and control the outputs of tri-linear color CCD arrays. Each channel
processes one color analog signal and includes an input clamp,
Correlated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), and a 16-bit A/D converter.
If there are sensors such as Contact Image Sensors (CIS) and
CMOS active pixel sensors, the CDS amplifiers are not necessary.
The 16-bit digital output is composed of high and low 8-bit
output and is assessed by two reading cycles. The internal registers
are programmed by a 3-wire serial interface which provides gain,
offset and operating mode adjustments.
The typical operation power of
M1008
is 400mW in 5V power
supply.
TSSOP-28
FEATURES
* 400mW In 5V Operation Supply
* Under 2mA Power-Down Mode
* Built-In16-Bit 30 Msps A/D Converter
* No Missing Codes
* Input Clamp Circuitry
* Correlated Double Sampling
* Programmable Gain
* 250mV Programmable Offset
* Built-In Voltage Reference
* Programmable 3-Wire Serial Interface
* 3V/5V Digital I/O Compatibility
* Up To 25 Msps In 1-Channel Operation
* Up To 30 Msps In 2-Channel (Even-Odd) Operation
* Up To 30 Msps In 3-Channel Operation
ORDERING INFORMATION
Ordering Number
M1008G-P28-T
M1008G-P28-R
Package
TSSOP-28
TSSOP-28
Packing
Tube
Tape Reel
M1008G-P28-T
(1) Packing Type
(2) Package Type
(3) Halogen Free
(1) T: Tube, R: Tape Reel
(2) P28: TSSOP-28
(3) G: Halogen Free
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QW-R502-434.a
M1008
PIN CONFIGURATIONS
Preliminary
CMOS IC
PIN DESCRIPTION
PIN NO.
PIN NAME
PIN TYPE
PIN DESCRIPTION
1
CDSCLK1
DI
CDS reference clock pulse input
2
CDSCLK2
DI
CDS data clock pulse input
3
ADCCLK
DI
A/D sample clock input for 3-channels mode
4
DI
Output enable, active low
OE
5
DRV
DD
P
Digital driver power
6
DRV
SS
P
Digital driver ground
7~14
D7~D0
DO
Digital data output
15
SDATA
DI/DO
Serial data input/output
16
SCLK
DI
Clock input for serial interface
17
SLOAD
DI
Serial interface load pulse
18,28
AV
DD
P
Analog supply
19,27
AV
SS
P
Analog ground
20
REFB
AO
Reference decoupling
21
REFT
AO
Reference decoupling
22
VINB
AI
Analog input, blue
23
CML
AO
Internal reference output
24
VING
AI
Analog input, green
25
OFFSET
AO
Clamp bias level decoupling
26
VINR
AI
Analog input, red
Note: I=input, O=output, I/O=input/output, P=power supply, G=ground
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M1008
BLOCK DIAGRAM
Preliminary
CMOS IC
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QW-R502-434.a
M1008
ABSOLUTE MAXIMUM RATING
Preliminary
CMOS IC
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
V
DD
V
SS
-0.3 to V
SS
+5.5
V
Input Voltage
V
IN
V
SS
-0.3 to V
DD
+0.3
V
Ambient Operation Temperature
T
OPR
-25 ~ +75
°C
Storage Temperature
T
STG
-50 ~ +125
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(AV
DD
=5V, DV
DD
=3V, T
A
=25°C. Unless otherwise specified)
PARAMETER
Analog Power Supply
Digital Power Supply
3-Channel Mode with CDS
2-Channel Mode with CDS
1-Channel Mode with CDS
ADC Resolution
Integral Nonlinear (INL)
Differential Nonlinear (DNL)
Offset Error
Gain Error
Full-Scale Input Range
Input Limits
Input Current
PGA Gain at Minimum
PGA Gain at Maximum
PGA Gain Resolution
Programmable Offset at Minimum
Programmable Offset at Maximum
Offset Resolution
Operating
Total Power Consumption
High Level Input Voltage
(CDSCLK1, CDSCLK2, ADCCLK,
OE
, SCK, SLOAD)
Low Level Input Voltage
(CDSCLK1, CDSCLK2, ADCCLK,
OE
, SCK, SLOAD)
High Level Input Voltage (SDATA)
Low Level Input Voltage (SDATA)
High Level Input Current
Low Level Input Current
Input Capacitance
High Level Output Voltage
(SDATA, D0~D7)
Low Level Output Voltage
(SDATA, D0~D7)
High Level Output Current
Low Level Output Current
SYMBOL
V
ADD
V
DRDD
t
MAX3
t
MAX2
t
MAX1
TEST CONDITION
MIN
4.75
3
30
30
25
TYP
5
5
MAX
5.25
5.25
UNIT
V
V
MSPS
MSPS
MSPS
Bits
LSB
LSB
mV
16
±32
-1
-100
R
FS
V
I(LIMIT)
I
IN
1
100
A
VSS
-0.3
T
A
P
tot
V
IH
0
%FSR
5
2.0
V
P-P
A
VDD
+0.3
5
V
10
nA
1
V/V
5.85
V/V
6
Bits
-250
mV
250
mV
9
Bits
70
°C
400
mW
0.8*V
DD
V
V
IL
V
IH1
V
IL1
I
IH
I
IL
C
IN
V
OH
V
OL
I
OH
I
OL
1
1
0.8*V
DD
0.2*V
DD
V
V
V
uA
uA
pF
V
0.2*V
DD
10
10
10
V
DD
-0.5
0.5
V
mA
mA
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QW-R502-434.a
M1008
TIMING SPECIFICATION
PARAMETER
3-Channel Pixel Rate
2-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Rising to CDSCLK1 Falling
ADCCLK Rising to CDSCLK2 Falling
Analog Sampling Delay
3-CHANNEL Mode Only
CDSCLK2 Falling to CDSCLK1 Rising
CDSCLK2 Falling to ADCCLK Rising
2-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Rising
CDSCLK2 Falling to CDSCLK1 Rising
1-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDARA Hold Time
Falling to SDATA Valid
DATA OUTPUT
Output Delay
Latency(Pipeline Delay)
Preliminary
SYMBOL
t
PRA
t
PRB
t
PRC
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC1
t
ADC2
t
AD
ta
C2C1
ta
C2ADR
tb
C2ADR
tb
C1ADR
tb
C2C1
tc
C2ADR
tc
C1ADF
tc
C2C1
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
t
OD
TEST CONDITION
MIN
100
66
40
16
12
12
0
0
0
5
30
30
30
15
15
20
0
15
10
10
10
10
10
10
8
9
TYP
CMOS IC
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
Cycles
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