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72V14071L15TFI

Description
FIFO, 8KX8, 10ns, Asynchronous, CMOS, PQFP64
Categorystorage    storage   
File Size149KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

72V14071L15TFI Overview

FIFO, 8KX8, 10ns, Asynchronous, CMOS, PQFP64

72V14071L15TFI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
Maximum access time10 ns
Maximum clock frequency (fCLK)66.7 MHz
JESD-30 codeS-PQFP-G64
JESD-609 codee0
memory density65536 bit
Memory IC TypeOTHER FIFO
memory width8
Humidity sensitivity level3
Number of terminals64
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX8
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP64,.47SQ,20
Package shapeSQUARE
Package formFLATPACK
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.01 A
Maximum slew rate0.04 mA
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
3.3 VOLT DUAL MULTIMEDIA FIFO
DUAL 256 x 8, DUAL 512 x 8
DUAL 1,024 x 8, DUAL 2,048 x 8
DUAL 4,096 x 8
IDT72V10071, IDT72V11071
IDT72V12071, IDT72V13071
IDT72V14071
FEATURES
DESCRIPTION
The IDT72V10071/72V11071/72V12071/72V13071/72V14071 are dual
Multimedia FIFOs. The device is functionally equivalent to two independent
FIFOs in a single package with all associated control, data, and flag lines
assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) has a 8-bit input
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and a Write Enable pin (WENA,
WENB).
Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate Write Enable pin is asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and Read Enable pin (RENA,
RENB).
The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual clock operation. An Output Enable pin
(OEA,
OEB)
is provided on the read port of each FIFO for three-state output
control.
Each of the two FIFOs has two fixed flags, Empty (EFA,
EFB)
and Full (FFA,
FFB).
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
Memory organization:
IDT72V10071
Dual 256 x 8
IDT72V11071
Dual 512 x 8
IDT72V12071
Dual 1,024 x 8
IDT72V13071
Dual 2,048 x 8
IDT72V14071
Dual 4,096 x 8
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
15 ns read/write cycle time
5V input tolerant
Separate control lines and data lines for each FIFO
Separate Empty and Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)
Industrial temperature range (–40°C to +85°C)
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
WRITE
CONTROL
READ
CONTROL
RCLKA
RENA
OEA
D
A0
- D
A7
Data In
x8
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
RESET LOGIC
Q
A0
- Q
A7
Data Out
x8
FLAG OUTPUTS
RSA
EFA
FFA
WCLKB
WENB
WRITE
CONTROL
READ
CONTROL
RCLKB
RENB
OEB
D
B0
- D
B7
Data In
x8
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
Q
B0
- Q
B7
Data Out
x8
RESET LOGIC
FLAG OUTPUTS
RSB
EFB
FFB
6360 drw01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2004 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.
DECEMBER 2004
DSC-6360/3
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