AK2363 datasheet, PDF - EEWORLD Datasheet

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AK2363: DescriptionRadio Signaling LSI; CategoryWireless rf/communication Telecom circuit; File Size556KB，33 Pages; ManufacturerAKM [Asahi Kasei Microsystems]

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AK2363 Overview

Radio Signaling LSI

AK2363 Parametric

Parameter Name	Attribute value
Maker	AKM [Asahi Kasei Microsystems]
Parts packaging code	QFN
package instruction	4 X 4 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFNJ-24
Contacts	24
Reach Compliance Code	unknow
power supply	3 V
Certification status	Not Qualified

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ASAHI KASEI

[AK2363]

AK2363

Radio Signaling LSI

Features

□

DTMF Receiver including an AGC circuit

Built-in MSK modem allowing selection from 1200 and 2400 bit/s

Programmable modem frame detection pattern

Built-in 3.6864MHz oscillator circuit

Support of external clocks with frequencies twice, three times, and four times

higher than 3.6864MHz

Operating voltage range:

2.6V to 3.7V

-40°C to +85°C

Operating temperature range:

Package:

24-pin QFNJ (4.0 x 4.0 x 0.75mm, 0.5mm pitch)

Overview

The AK2363 is a radio signaling LSI device into which an MSK modem and a DTMF Receiver are

integrated on a single chip.

The MSK modem supports 1200 and 2400 bit/s, and the demodulator has a 16-bit frame pattern

detection function that allows any settings. When the signal-to-noise (S/N) ratio is 12dB, the BER

characteristic at 1200 bit/s is 5.0E-06, and the BER characteristic at 2400 bit/s is 1.0E-04.

The DTMF Receiver operates in two modes: Normal mode (AGD Disable) indicating input signal

detection levels ranging from -27dBx to 0dBx and high sensitivity mode (AGC Enable) in which the

receiver operates at –40dBx to 0dBx.

In addition to a fundamental frequency of 3.686MHz, the oscillator circuit supports external clock input

with frequencies of 7.3728MHz (twice higher than 3.6864MHz), 11.0592MHz (three times higher than

3.6864MHz), and 14.7456MHz (four times higher than 3.6864MHz).

The internal operation is controlled by the three-wire serial method in which serial input data (SDATA)

consisting of a 1-bit instruction, a 4-bit address, and 8-bit data is set in synchronization with the CSN

and SCLK signals.

The 24-pin QFNJ package (4.0mm

4.0mm) is employed to realize compact, high-density packaging.

MS0583-E-01

-1-

2008/06

ASAHI KASEI

[AK2363]

Contents

Features ............................................................................................................................ 1

Overview ........................................................................................................................... 1

Contents ........................................................................................................................... 2

Block Diagram .................................................................................................................. 3

Pin Assignments .............................................................................................................. 3

Block Functions ............................................................................................................... 4

Pin Functions ................................................................................................................... 5

Absolute Maximum Ratings ............................................................................................ 7

Recommended Operating Conditions............................................................................ 7

Digital DC Characteristics ............................................................................................... 7

Clock Input Characteristics ............................................................................................ 8

System Reset ................................................................................................................... 8

Current Consumption ...................................................................................................... 9

Analog Characteristics .................................................................................................. 10

Digital AC Timing ........................................................................................................... 11

Register Functions ........................................................................................................ 17

MSK Modem Operation ................................................................................................. 22

DTMF Receiver Operation ............................................................................................. 25

Recommended External Circuit Examples .................................................................. 29

Package .......................................................................................................................... 32

Important Notice ............................................................................................................ 33

MS0583-E-01

-2-

2008/06

ASAHI KASEI

[AK2363]

Block Functions

Block

MSK Modulator

MSK DAC

Function

This circuit generates an MSK signal according to the logic of a digital signal input

from the TDATA pin.

DAC that converts data generated by the MSK Modulator into an analog signal.

This circuit is a low-pass filter for eliminating the clock component included in the

MSK DAC signal.

A switch for changing between the mute and active states is provided between this

filter and VR and is set by setting register MSKTX.

This control adjusts the output level of the transmit MSK signal.

Setting register: VR[4:0] Adjustment range: -6.0dB to +6.0dB in 0.5dB steps

Operational amplifier for gain adjustment of the transmit MSK signal and for forming

a smoothing filter for removing noise components included in the output signal.

Use an external resistor and capacitor to set the gain to 0dB and the cut-off

frequency to around 13kHz.

Operational amplifier for gain adjustment of the receive demodulation signal and for

forming a filter for preventing aliasing noise in the SCF circuit in the subsequent

stage. Use external resistors and capacitors to set the gain to 20dB or less and the

cut-off frequency to around 40kHz.

Band-pass filter to eliminate out-of-band components included in the receive MSK

signal.

This circuit demodulates the MSK signal and generates data.

This circuit detects the carrier signal from the MSK signal and regenerates a clock

signal.

AGC (Auto Gain Control) circuit for adjusting the input level of the DTMF signal

automatically.

Setting register: AGCSW or AGCSW. When disabled, this circuit functions as a

PGA (Programmable Gain Amp) circuit.

Setting register: PGA[1:0] Adjustment range: 0dB to +12dB in 4dB steps

A switch for changing the input is provided between this circuit and RXA and is set

by setting register DTMFSL.

DTMF signal detection circuit. It decodes the input signal and outputs 4-bit code.

This circuit generates a 3.6864MHz reference clock signal from an external crystal

oscillator and resistor.

When a signal of which frequency is twice, three times, or four times higher than

3.6864MHz is input from the outside, this circuit divides the signal frequency by two,

three, or four.

Setting register: MCKSL[1:0]

This circuit generates the reference voltage (1/2VDD) for internal analog signals.

Control registers set the switches and control in the IC according to the serial input

data consisting of a 1-bit instruction, a 4-bit address, and 8-bit data. A built-in data

buffer is provided to hold 8-bit MSK receive data for easier interfacing with the CPU.

At power-on, a system reset is caused by the RSTN pin. A soft reset is set by the

SRST register. (Refer to the description of the registers.)

MSK LPF

TXA

RXA

MSK BPF

Data Demodulator

Digital PLL

AGC(PGA)

DTMF Receiver

OSC

DIV (1/2,1/3,1/4)

AGND

Control

MS0583-E-01

-4-

2008/06

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