[AK4686]
AK4686
Multi-channel CODEC with Capless Stereo Selector
GENERAL DESCRIPTION
The AK4686 is a single chip audio CODEC that includes one stereo ADC and two stereo DACs in addition
to the input selector and the line drivers. The interfaces of ADC/DAC can accept up to 24bit input data and
support asynchronous operation. Both the input stereo selector and output drivers support ground
reference I/O to remove AC-coupling capacitors and reducing external parts. The AK4686 has a dynamic
range of 96dB for ADC, 100dB for DAC, and it is well suitable for digital TV and Home theater systems.
FEATURES
Asynchronous Operation between Port 1(ADC and DAC1) and Port 2 (DAC2)
6:1 Capless Stereo Line Input Selector
24bit Stereo ADC
- 64x Oversampling
- Sampling Rate up to 48kHz
- Linear Phase Digital Anti-Alias Filter
- S/(N+D): 88dB
- Dynamic Range, S/N: 96dB
- Digital HPF for Offset Cancellation
24bit Two Stereo DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- S/(N+D): 88dB
- Dynamic Range, S/N: 100dB
- De-emphasis Filter
- Analog Soft Mute
High Jitter Tolerance
TTL Level Digital I/F
External Master Clock Input:
256fs, 384fs, 512fs 768fs (fs=32kHz
∼
48kHz)
128fs, 192fs, 256fs 384fs (fs=64kHz
∼
96kHz)
128fs, 192fs (fs=128kHz ~ 192kHz)
2 Audio Serial I/F (PORT1, PORT2)
- Master/Slave mode (PORT1)
- I/F format
PORT2: MSB, LSB justified (16/24 bit), I2S
PORT1: MSB, LSB justified (16/24 bit), I2S
2
I C Bus
μP
I/F for mode setting
Operating Voltage:
- Digital I/O: 3.0V
∼
3.6V
- Charge Pump: 3.0V
∼
3.6V
- Analog: 3.0V
∼
3.6V
Package: 48pinLQFP
MS1243-E-01
-1-
2010/10
[AK4686]
2Vrms
PWAD bit
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
PWDA1 bit
PORT1
2ch
ADC
HPF
MCLK1
BICK1
LRCK1
SDTO1
SDTI1
MS1
Serial
I/F
2Vrms
LOUT1
2ch
DAC
ROUT1
PWAD bit or PWDA1 bit
Control
PDN pin
Analog Soft Mute
Analog Soft Mute
PWDA2 bit
PORT2
LOUT2
I/F
CVEE
CP
CN
Charge
Pump
SDA
SCL
MT1N
MT2N
PDN
2ch
DAC
ROUT2
Serial
I/F
MCLK2
BICK2
LRCK2
SDTI2
AVDD1
VSS1
CVDD
VSS2
AVDD2
VSS3
DVDD
VSS4
CAD1
CAD0
AK4686 Block Diagram
MS1243-E-01
-2-
2010/10
[AK4686]
■
Ordering Guide
AK4686EQ
AKD4686
-20
∼
+85°C
48pin LQFP (0.5mm pitch)
Evaluation Board for the AK4686
■
Pin Layout
LRCK1
BICK1
MCLK1
SDTO
SDTI1
DVD D
MT1N
36 3 5 34 33 32 31 30 29 2 8 27 2 6 2 5
LIN1
RIN1
NC
LIN2
RIN2
NC
LIN3
RIN3
NC
LIN4
RIN4
NC
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
1 0 11 12
Top Vie w
24
23
22
NC
BICK2
MCL K2
LRC K2
SDTI2
PDN
CVDD
CP
VSS3
CN
CVEE
VSS2
MS1
SCL
MT2N
21
20
19
18
17
16
15
14
13
AVDD2
AK4686EQ
VSS4
SD A
LOUT2
RIN5
VSS1
LIN6
LOUT1
LIN5
MS1243-E-01
-3-
ROUT1
ROUT2
AVDD1
NC
RIN6
2010/10
[AK4686]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin Name
LIN5
RIN5
NC
LIN6
RIN6
AVDD1
VSS1
LOUT1
ROUT1
LOUT2
ROUT2
AVDD2
VSS2
CVEE
CN
VSS3
CP
CVDD
PDN
SDTI2
LRCK2
MCLK2
BICK2
NC
MT2N
MS1
SDTI1
MCLK1
MT1N
DVDD
VSS4
SDTO
LRCK1
BICK1
SDA
SCL
LIN1
RIN1
NC
LIN2
RIN2
NC
I/O
I
I
-
I
I
-
-
O
O
O
O
-
-
O
I
-
I
-
I
I
I
I
I
-
I
I
I
I
I
-
-
O
I/O
I/O
I/O
I
I
I
-
I
I
-
Function
Lch Input 5 Pin
Rch Input 5 Pin
This pin must be connected to the ground.
Lch Input 6 Pin
Rch Input 6 Pin
ADC&DAC1 Analog Power Supply Pin, 3.0V∼3.6V
ADC&DAC1 Analog Ground Pin, 0V
Lch Analog Output Pin1
Rch Analog Output Pin1
Lch Analog Output Pin2
Rch Analog Output Pin2
DAC2 Analog Power Supply Pin, 3.3V∼3.6V
DAC2 Analog Ground Pin, 0V
Charge Pump Circuit Negative Voltage Output Pin (for Analog Input/Output)
Negative Charge Pump Capacitor Terminal Pin (for Analog Input/Output)
Charge Pump Circuit Analog Ground Pin, 0V (for Analog Input/Output)
Positive Charge Pump Capacitor Terminal Pin (for Analog Input/Output)
Charge Pump Circuit Positive Power Supply Pin 3.0V∼3.6V (for Analog Input/Output)
Power-Down Mode & Reset Pin
When “L”, the AK4686 is powered-down, all registers are reset. And then all digital
output pins go “L”. The AK4686 must be reset once upon power-up.
Audio Serial Data Input Pin (for PORT2)
Input Channel Clock Pin (for PORT2)
DAC2 Master Clock Input Pin (for PORT2)
Audio Serial Data Clock Pin (for PORT2)
This pin must be connected to the ground.
DAC2 Mute Pin
“H”: Normal Operation
“L”: Mute
PORT1 Master Mode Select Pin.
“L”(connected to the ground): Slave mode.
“H”(connected to DVDD) : Master mode.
Audio Serial Data Input Pin (for PORT1)
ADC&DAC1 Master Clock Input Pin (for PORT1)
DAC1 Mute Pin
“H”: Normal Operation
“L”: Mute
Digital Power Supply Pin, 3.0V∼3.6V
Digital Ground Pin, 0V
Audio Serial Data Output 1 Pin (for PORT1)
Channel Clock 1 Pin (for PORT1)
Audio Serial Data Clock 1 Pin (for PORT1)
Control Data Pin
Control Data Clock Pin
Lch Input 1 Pin
Rch Input 1 Pin
This pin must be connected to the ground.
Lch Input 2 Pin
Rch Input 2 Pin
This pin must be connected to the ground.
MS1243-E-01
-4-
2010/10
[AK4686]
PIN/FUNCTION (Continued)
No.
Pin Name I/O
Function
43
LIN3
I
Lch Input 3 Pin
44
RIN3
I
Rch Input 3 Pin
45
NC
-
This pin must be connected to the ground.
46
LIN4
I
Lch Input 4 Pin
47
RIN4
I
Rch Input 4 Pin
48
NC
-
This pin must be connected to the ground.
Note: All digital input pins must not be left floating.
■
Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification
Analog
Digital
Pin Name
LOUT1-2, ROUT1-2, LIN1-6, RIN1-6
SDTO1, LRCK1(Master), BICK1(Master)
MCLK1-2, LRCK1(Slave), LRCK2, BICK1(Slave),
BICK2, SDTI1-2, MS1, CAD0
SDA, SCL, MT1N, MT2N
-
NC
Setting
These pins must be open.
These pins must be open.
These pins must be connected to VSS4.
These pins must be pulled-up to DVDD.
These pins should be connected to the ground.
MS1243-E-01
-5-
2010/10
京公网安备 11010802033920号
EEWORLD
