TS87C52X2-LCAD datasheet, PDF - EEWORLD Datasheet

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TS87C52X2-LCAD: Description8-bit CMOS Microcontroller 0-60 MHz; CategoryThe embedded processor and controller Microcontrollers and processors; File Size253KB，54 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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TS87C52X2-LCAD Overview

8-bit CMOS Microcontroller 0-60 MHz

TS87C52X2-LCAD Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	TEMIC
Reach Compliance Code	unknow
bit size	8
CPU series	8051
JESD-30 code	R-PDIP-T40
JESD-609 code	e0
Number of terminals	40
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	256
rom(word)	8192
ROM programmability	UVPROM
speed	40 MHz
Maximum slew rate	13 mA
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL

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TS80C52X2

8-bit CMOS Microcontroller 0-60 MHz

1. Description

TEMIC TS80C52X2 is high performance CMOS ROM,

OTP, EPROM and ROMless versions of the 80C51

CMOS single chip 8-bit microcontroller.

The TS80C52X2 retains all features of the TEMIC

80C51 with extended ROM/EPROM capacity (8

Kbytes), 256 bytes of internal RAM, a 6-source , 4-level

interrupt system, an on-chip oscilator and three timer/

counters.

In addition, the TS80C52X2 has a dual data pointer, a

more versatile serial channel that facilitates

multiprocessor communication (EUART) and a X2 speed

improvement mechanism.

The fully static design of the TS80C52X2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TS80C52X2 has 2 software-selectable modes of

reduced activity for further reduction in power

consumption. In the idle mode the CPU is frozen while

the timers, the serial port and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

2. Features

80C52 Compatible

•

8051 pin and instruction compatible

•

Four 8-bit I/O ports

•

Three 16-bit timer/counters

•

256 bytes scratchpad RAM

Interrupt Structure with

•

6 Interrupt sources,

•

4 level priority interrupt system

Full duplex Enhanced UART

•

Framing error detection

•

Automatic address recognition

High-Speed Architecture

•

40 MHz @ 5V, 30MHz @ 3V

•

X2 Speed Improvement capability (6 clocks/

machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

Low EMI (inhibit ALE)

Power Control modes

•

Idle mode

•

Power-down mode

•

Power-off Flag

Dual Data Pointer

On-chip ROM/EPROM (8K-bytes)

Programmable Clock Out and Up/Down Timer/

Counter 2

Asynchronous port reset

Once mode (On-chip Emulation)

Power supply: 4.5-5V, 2.7-5.5V

Temperature ranges: Commercial (0 to 70

C) and

Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1

(13.9 footprint), CQPJ44 (window), CDIL40

(window)

Rev. B - Jan. 25, 1999

Preliminary

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