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SY100EL92ZI

Description
TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size58KB,5 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric Compare View All

SY100EL92ZI Overview

TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20

SY100EL92ZI Parametric

Parameter NameAttribute value
MakerMicrochip
package instructionSOIC-20
Reach Compliance Codecompli
ECCN codeEAR99
Date Of I2016-11-04
maximum delay0.63 ns
Interface integrated circuit typePECL TO LVPECL TRANSCEIVER
JESD-30 codeR-PDSO-G20
length12.83 mm
Number of digits1
Number of functions3
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output latch or registerNONE
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Maximum seat height2.65 mm
Maximum slew rate12 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width7.52 mm
Micrel, Inc.
TRIPLE LVPECL-TO-PECL
OR PECL-TO-LVPECL TRANSLATOR
SY100EL92
SY100EL92
FEATURES
s
5V and 3.3V power supplies required
s
Also, supports LVPECL-to-PECL translation
s
500ps propagation delays
s
Fully differential design
s
Differential line receiver capability
s
Application note
s
Available in 20-pin SOIC package
DESCRIPTION
The SY100EL92 is a triple LVPECL-to-PECL or PECL-
to-LVPECL translator. The device receives standard PECL
signals and translates them to differential LVPECL output
signals (or vice versa). SY100EL92 can also be used as a
differential line receiver for PECL-to-PECL or LVPECL-to-
LVPECL signals. However, please note that for the latter
we will need two different power supplies. Please refer to
Function Table for more details.
V
BB
outputs are provided for interfacing single ended
input signals. If a single ended input is to be used, the V
BB
output should be connected to the D input and the active
signal will drive the D input. When used, the V
BB
should be
bypassed to V
CC
via a 0.01µF capacitor. The V
BB
is
designed to act as a switching reference for the SY100EL92
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
To accomplish the PECL-to-LVPECL level translation,
the SY100EL92 requires three power rails. The V
CC
and
V
CC
_V
BB
supply is to be connected to the standard PECL
supply, the 3.3V supply is to be connected to the V
CCO
supply, and GND is connected to the system ground plane.
Both the V
CC
and V
CCO
should be bypassed to ground with
a 0.01µF capacitor.
To accomplish the LVPECL-to-PECL level translation,
the SY100EL92 requires three power rails as well. The 5.0V
supply is connected to the V
CC
and V
CCO
pins, 3.3V supply
is connected to the V
CC
_V
BB
pin and GND is connected to
the system ground plane. V
CC
_V
BB
is used to provide a
proper V
BB
output level if a single ended input is used. For
differential LVPECL input V
CC
_V
BB
can be either 3.3V or
5V.
Under open input conditions, the D input will be biased
at a V
CC
/2 voltage level and the D input will be pulled to
GND. This condition will force the "Q" output low, ensuring
stability.
FUNCTION TABLE
Function
PECL-to-LVPECL
LVPECL-to-PECL
PECL-to-PECL
LVPECL-to-LVPECL
Vcc
5.0V
5.0V
5.0V
5.0V
Vcco
3.3V
5.0V
5.0V
3.3V
Vcc_V
BB
5.0V
3.3V
5.0V
3.3V
PIN NAMES
Pin
Dn
Q
n
V
BB
V
CCO
V
CC
_V
BB
GND
V
CC
Function
PECL / LVPECL Inputs
PECL / LVPECL Outputs
PECL / LVPECL Reference Voltage Output
V
CC
for Output
V
CC
for V
BB
Output
Common Ground Rail
V
CC
for Internal Circuitry
M9999-031306
hbwhelp@micrel.com or (408) 955-1690
Rev.: G
Amendment: /0
1
1
Issue Date: March 2006

SY100EL92ZI Related Products

SY100EL92ZI SY100EL92ZGTR SY100EL92ZITR SY100EL92_06
Description TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20 TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20 TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20 TRIPLE PECL TO LVPECL TRANSCEIVER, COMPLEMENTARY OUTPUT, PDSO20
Number of digits 1 1 1 1
Number of functions 3 3 3 3
Number of terminals 20 20 20 20
Maximum operating temperature 85 °C 85 °C 85 °C 85 Cel
Minimum operating temperature -40 °C -40 °C -40 °C -40 Cel
Output latch or register NONE NONE NONE NONE
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
surface mount YES YES YES Yes
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL DUAL
package instruction SOIC-20 SOP, SOP20,.4 SOIC-20 -
Reach Compliance Code compli compli compli -
ECCN code EAR99 EAR99 EAR99 -
maximum delay 0.63 ns 0.63 ns 0.63 ns -
Interface integrated circuit type PECL TO LVPECL TRANSCEIVER PECL TO LVPECL TRANSCEIVER PECL TO LVPECL TRANSCEIVER -
JESD-30 code R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 -
length 12.83 mm 12.83 mm 12.83 mm -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code SOP SOP SOP -
Encapsulate equivalent code SOP20,.4 SOP20,.4 SOP20,.4 -
Package shape RECTANGULAR RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE -
Maximum seat height 2.65 mm 2.65 mm 2.65 mm -
Maximum slew rate 12 mA 12 mA 12 mA -
Maximum supply voltage 5.5 V 5.5 V 5.5 V -
Minimum supply voltage 4.5 V 4.5 V 4.5 V -
Nominal supply voltage 5 V 5 V 5 V -
Terminal pitch 1.27 mm 1.27 mm 1.27 mm -
width 7.52 mm 7.62 mm 7.52 mm -
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