SY10EL34ZGTR datasheet, PDF - EEWORLD Datasheet

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SY10EL34ZGTR: Description5V/3.3V Ã·2, Ã·4, Ã·8 Clock Generation Chip; Categorylogic logic; File Size167KB，7 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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SY10EL34ZGTR Overview

5V/3.3V Ã·2, Ã·4, Ã·8 Clock Generation Chip

SY10EL34ZGTR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
Parts packaging code	SOIC
package instruction	SOIC-16
Contacts	16
Reach Compliance Code	compli
series	10EL
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	9.93 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	6
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	1.2 ns
Same Edge Skew-Max（tskwd）	0.05 ns
Maximum seat height	1.73 mm
surface mount	YES
technology	ECL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.94 mm

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SY10EL34/L

SY100EL34/L

5V/3.3V

÷2, ÷4, ÷8

Clock Generation Chip

Precision Edge

General Description

The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock

generation chips designed explicitly for low-skew clock

generation applications. The internal dividers are

synchronous to each other; therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the V

output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the V

output should be connected to the

CLK

input and bypassed to ground via a 0.01µF capacitor. The

output is designed to act as the switching reference for

the input of the EL34/L under single-ended input

conditions. As a result, this pin can only source/ sink up to

0.5mA of current.

The common enable (

) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids any

chance of generating a runt clock pulse on the internal

clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could

lead to losing synchronization between the internal divider

stages. The internal enable flip-flop is clocked on the

falling edge of the divider stages. The internal enable flip-

flop is clocked on the falling edge of the input clock;

therefore, all associated specification limits are referenced

to the negative edge of the clock input.

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL34/Ls in a system.

Data sheets and support documentation can be found on

Micrel’s web site at:

www.micrel.com.

Precision Edge

Features

•

3.3V and 5V power supply options

50ps output-to-output skew

Synchronous enable/disable

Master Reset for synchronization

Internal 75KΩ input pull-down resistors

Available in 16-pin SOIC package

Pin Description

Pin Name

CLK

Pin Function

Differential clock inputs.

Synchronous enable.

Master reset.

Reference output.

Differential

÷2

outputs.

Differential

÷4

outputs.

Differential

÷8

outputs.

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (

408

) 944-0800 • fax + 1 (408) 474-1000 •

http://www.micrel.com

December 2011

M9999-120611-I

hbwhelp@micrel.com

or (408) 955-1690

SY10EL34ZGTR Related Products

	SY10EL34ZGTR	SY100EL34ZGTR	SY10EL34ZG	SY10EL34_11
Description	5V/3.3V Ã·2, Ã·4, Ã·8 Clock Generation Chip	5V/3.3V Ã·2, Ã·4, Ã·8 Clock Generation Chip	5V/3.3V Ã·2, Ã·4, Ã·8 Clock Generation Chip	5V/3.3V Ã·2, Ã·4, Ã·8 Clock Generation Chip
Is it Rohs certified?	conform to	conform to	conform to	-
Maker	Microchip	Microchip	Microchip	-
package instruction	SOIC-16	SOP,	SOIC-16	-
Reach Compliance Code	compli	compli	compli	-
series	10EL	100EL	10EL	-
Input adjustment	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	-
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	-
JESD-609 code	e4	e4	e4	-
length	9.93 mm	9.93 mm	9.93 mm	-
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	-
Number of functions	1	1	1	-
Number of terminals	16	16	16	-
Actual output times	6	6	3	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	SOP	SOP	SOP	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	-
propagation delay (tpd)	1.2 ns	1.2 ns	1.2 ns	-
Same Edge Skew-Max（tskwd）	0.05 ns	0.05 ns	0.05 ns	-
Maximum seat height	1.73 mm	1.73 mm	1.73 mm	-
surface mount	YES	YES	YES	-
technology	ECL	ECL	ECL	-
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	-
Terminal form	GULL WING	GULL WING	GULL WING	-
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	-
Terminal location	DUAL	DUAL	DUAL	-
width	3.94 mm	3.94 mm	3.94 mm	-

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