Preliminary
Datasheet
R1EX24064ASAS0I
R1EX24064ATAS0I
Two-wire serial interface
64k EEPROM (8-kword
8-bit)
Description
R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They
realize high speed, low power consumption and a high level of reliability by employing advanced MONOS memory
technology and CMOS process and low voltage circuitry technology. They also have a 32-byte page programming
function to make their write operation faster.
R10DS0100EJ0100
Rev.1.00
Aug. 29, 2011
Features
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I
2
C serial bus)
Clock frequency: 400 kHz
Power dissipation:
Standby: 2
A
(max)
Active (Read): 1 mA (max)
Active (Write): 3.0 mA (max)
Automatic page write: 32-byte/page
Write cycle time: 5 ms
Endurance: 1,000k Cycles @ 25C
Data retention: 100 Years @ 25C
Small size packages: SOP-8pin, TSSOP-8pin
Shipping tape and reel
TSSOP 8-pin: 3,000 IC/reel
SOP 8-pin: 2,500 IC/reel
Temperature range:
40
to +85C
Lead free products.
R10DS0100EJ0100 Rev.1.00
Aug. 29, 2011
Page 1 of 16
R1EX24064ASAS0I/R1EX24064ATAS0I
Preliminary
Ordering Information
Orderable Part Numbers
R1EX24064ASAS0I#S0
Internal organization
64k bit (8192
8-bit)
Package
150 mil 8-pin plastic SOP
PRSP0008DF-B (FP-8DBV)
Lead free
8-pin plastic TSSOP
PTSP0008JC-B (TTP-8DAV)
Lead free
Shipping tape and reel
2,500 IC/reel
R1EX24064ATAS0I#S0
64k bit (8192
8-bit)
3,000 IC/reel
Pin Arrangement
8-pin SOP /8-pin TSSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
(Top view)
V
CC
WP
SCL
SDA
Pin Description
Pin name
A0 to A2
SCL
SDA
WP
V
CC
V
SS
Device address
Serial clock input
Serial data input/output
Write protect
Power supply
Ground
Function
Block Diagram
V
CC
V
SS
Address generator
High voltage generator
X decoder
Memory array
WP
A0, A1, A2
SCL
SDA
Control
logic
Y decoder
Y-select & Sense amp.
Serial-parallel converter
R10DS0100EJ0100 Rev.1.00
Aug. 29, 2011
Page 2 of 16
R1EX24064ASAS0I/R1EX24064ATAS0I
Preliminary
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Input voltage relative to V
SS
Operating temperature range*
1
Storage temperature range
Symbol
V
CC
Vin
Topr
Tstg
Value
–0.6 to +7.0
–0.5*
2
to +7.0*
3
–40 to +85
–55 to +125
Unit
V
V
C
C
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): –3.0 V for pulse width
50 ns.
3. Should not exceed V
CC
+ 1.0 V.
DC Operating Conditions
Parameter
Supply voltage
Input high voltage
Input low voltage
Operating temperature
Note:
Symbol
V
CC
V
SS
V
IH
V
IL
Topr
Min
1.8
0
V
CC
0.7
–0.3*
1
–40
Typ
—
0
—
—
—
Max
5.5
0
V
CC
+ 0.5
V
CC
0.3
+85
Unit
V
V
V
V
C
1. V
IL
(min): –1.0 V for pulse width
50 ns.
DC Characteristics
(Ta = –40 to +85°C, V
CC
= 1.8 V to 5.5 V)
Parameter
Input leakage current
Output leakage current
Standby V
CC
current
Read V
CC
current
Write V
CC
current
Output low voltage
Symbol
I
LI
I
LO
I
SB
I
CC1
I
CC2
V
OL2
V
OL1
Min
—
—
—
—
—
—
—
Typ
—
—
1.0
—
—
—
—
Max
2.0
2.0
2.0
1.0
3.0
0.4
0.2
Unit
A
A
A
mA
mA
V
V
Test conditions
V
CC
= 5.5 V, Vin = 0 to 5.5 V
V
CC
= 5.5 V, Vout = 0 to 5.5 V
Vin = V
SS
or V
CC
V
CC
= 5.5 V, Read at 400 kHz
V
CC
= 5.5 V, Write at 400 kHz
V
CC
= 2.7 to 5.5 V, I
OL
= 3.0 mA
V
CC
= 1.8 to 2.7 V, I
OL
= 1.5 mA
Capacitance
(Ta = +25C, f = 1 MHz)
Parameter
Input capacitance (A0 to A2, SCL, WP)
Output capacitance (SDA)
Note:
1. Not 100 tested.
Symbol
Cin*
1
C
I/O
*
1
Min
—
—
Typ
—
—
Max
6.0
6.0
Unit
pF
pF
Test conditions
Vin = 0 V
Vout = 0 V
Memory cell characteristics
(V
CC
= 1.8 V to 5.5 V)
Endurance
Data retention
Note:
1. Not 100 tested.
Ta=25C
1,000k Cycles min.
100 Years min.
Ta=85C
100k Cycles min
10 Years min.
Notes
1
1
R10DS0100EJ0100 Rev.1.00
Aug. 29, 2011
Page 3 of 16
R1EX24064ASAS0I/R1EX24064ATAS0I
Preliminary
AC Characteristics
Test Conditions
Input pules levels:
V
IL
= 0.2
V
CC
V
IH
= 0.8
V
CC
Input rise and fall time:
20 ns
Input and output timing reference levels: 0.5
V
CC
Output load: TTL Gate + 100 pF
(Ta = –40 to +85°C, V
CC
= 1.8 V to 5.5 V)
Parameter
Clock frequency
Clock pulse width low
Clock pulse width high
Noise suppression time
Access time
Bus free time for next mode
Start hold time
Start setup time
Data in hold time
Data in setup time
Input rise time
Input fall time
Stop setup time
Data out hold time
Write protect hold time
Write protect setup time
Write cycle time
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
HD.WP
t
SU.WP
t
WC
Min
—
1200
600
—
100
1200
600
600
0
100
—
—
600
50
1200
0
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
400
—
—
50
900
—
—
—
—
—
300
300
—
—
—
—
5
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes
1
1
1
2
Notes: 1. Not 100% tested.
2. t
WC
is the time from a stop condition to the end of internally controlled write cycle.
R10DS0100EJ0100 Rev.1.00
Aug. 29, 2011
Page 4 of 16
R1EX24064ASAS0I/R1EX24064ATAS0I
Preliminary
Timing Waveforms
Bus Timing
1/f
SCL
t
LOW
t
F
SCL
t
SU.STA
t
HD.STA
SDA
(in)
t
AA
SDA
(out)
t
SU.WP
WP
t
HIGH
t
R
t
HD.DAT
t
SU.DAT
t
SU.STO
t
BUF
t
DH
t
HD.WP
Write Cycle Timing
Stop condition
Start condition
SCL
SDA
D0 in
Write data
(Address (n))
ACK
t
WC
(Internally controlled)
R10DS0100EJ0100 Rev.1.00
Aug. 29, 2011
Page 5 of 16
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