New Product
R2A20162NS/SA/SP
8-bit 2ch D/A Converter with Buffer
R03DS0016EJ0100
Rev.1.00
2011.09.05
Description
The R2A20162 is an integrated circuit semiconductor of CMOS structure with 2 channels of built in D/A
converters with output buffer op-amps. It is the electrical characteristic improvement version of the M62342.
Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD.
Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and
can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements
unnecessary and enabling configuration of a system with few component parts.
Very small SON package is added to lineup. It is suitable for a small mounting and reduces the mounting area.
Features
Guarantee Differential Nonlinearity error : +/- 0.7LSB, Nonlinearity error : +/- 1.0LSB,
Data transfer format: 10-bit serial data input type by 3 wire ( DI, SCK, LD )
Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V )
High output current capacity: +/- 1mA or Higher
Very mall size package line-up: SON-8 (pin pitch: 0.5mm), TSSOP-8 (pin pitch 0.65mm)
Application
Conversion from digital data to analog control data for home-use and industrial equipment.
Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor.
Blurring correction control or various control of the interchangeable lens of digital camera for self
adjustment by combination with microcomputer and EEPROM. (substitution of half fixed resistance)
Block Diagram
Vcc
4
LD
8
CLK
7
DI
6
GND
5
10-bit shift register
Power on
reset
8
Channel
decoder
8-bit latch
8-bit upper
segment R-2R
8-bit latch
8-bit upper
Segment R-2R
1
Ao1
R03DS0016EJ0100 Rev.1.00
2011.09.05
2
Ao2
3
N.C.
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R2A20162NS/SA/SP
New Product
Pin Arrangement
R2A20162NS (Top view)
R2A20162SA/SP (Top view)
Ao1 1
Ao2 2
N.C. 3
Vcc 4
8 LD
7 CLK
6 DI
5 GND
N.C.: Not connected
Ao1 1
Ao2 2
N.C. 3
Vcc
4
8 LD
7 CLK
6 DI
5 GND
N.C.: Not connected
Outline: PWSN0008KA-A [NS]
Outline: PRSP0008DE-C [SP]
PTSP-0008JC-B [SA]
Pin Description
Pin No.
6
Pin Name
DI
Function
Serial data input terminal.
(Input serial data with a 10-bit data length.)
Serial clock input terminal
(Input signal from DI terminal is input to 10-bit shift register at rise of serial
clock.)
Load terminal
(When High level is input to LD terminal, value in 10-bit shift register is
loaded into decoder and 8-bit latch.)
8-bit resolution D/A converter output terminals
(After power-on, all channels are reset and DAC data 00h is output.)
Not connected
Power supply terminal
GND terminal
7
CLK
8
1
2
3
4
5
LD
Ao1
A02
N.C.
Vcc
GND
R03DS0016EJ0100 Rev.1.00
2011.09.05
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R2A20162NS/SA/SP
New Product
(Ta= +25deg unless otherwise noted)
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Buffer amplifier output current
Power dissipation
Thermal derating factor
Operating temperature
Storage temperature
Symbol
Vcc
Vin
Vo
I
AO
Pd
K theta
Topr
Tstg
Conditions
Ratings
-0.3 to +6.5
-0.3 to Vcc+0.3 <6.5
-0.3 to Vcc+0.3 <6.5
Unit
V
V
V
mA
mW
mW/deg
deg
deg
Continuous
Ta=85deg
Ta>25deg
-2.0 to +2.0
270(NS) / 200(SA) / 272(SP)
6.75(NS) / 5.0(SA) / 6.8(SP)
-30 to +85
-40 to +125
Electrical Characteristics
Item
Supply voltage
Supply current
Supply voltage rise-up time *1
Operating voltage of
Internal resetting
*1
Symbol
( Vcc= +5V +/-10%, GND=0V, Ta= -30 to +85deg unless otherwise noted)
Test Conditions
Limits
Min.
2.7
CLK = 1MHz operation, I
AO
=0µA,
DATA: 6Ah (at maximum current)
SDA = SCL = GND, I
AO
=0µA
Typ.
5.0
0.7
0.5
—
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
Max.
5.5
2.5
1.6
—
1.9
—
10
0.2Vcc
Vcc
Vcc
Vcc-0.1
Vcc-0.2
1.0
0.7
1.0
2.0
2.0
0.1
—
Unit
V
mA
mA
µs
V
ms
µA
V
V
V
V
mA
LSB
LSB
LSB
LSB
µF
ohm
Vcc
Icc
tr
Vcc
Vcc
POR
t
POR
I
ILK
V
IL
V
IH
V
AO
I
AO
S
DL
S
L
S
ZERO
S
FULL
Co
Ro
0
0
100
—
1
-10
0
0.5Vcc
0.8Vcc
0.1
0.2
-1.0
-0.7
Vcc=0 to 2.7V
Vcc=0 to 2.7V
Vcc < 0.1V
VIN= 0 to Vcc
Time period of re-power on
(Power supply OFF
ON) *1
Input leak current
Input low voltage
Input high voltage
Buffer amplifier output voltage
range
Buffer amplifier output drive
range
Differential nonlinearity
Nonlinearity
Zero code error
Full scale error
Output capacitate load
Buffer amplifier output
impedance
4.0V < Vcc
Vcc < 4.0V
I
AO
= +/-100µA
I
AO
= +/-500µA
Upper side saturation voltage = 0.3V
Lower side saturation voltage = 0.2V
Vcc=5.12V (20mV/ LSB),
without load (I
AO
= 0µA)
-1.0
-2.0
-2.0
—
—
*1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly,
initialize is not operate. So, keep the time period of re-powered on (t
POR
).
tr
Vcc
t
POR
(equivalent to tr
Vcc
)
Vcc
Vcc
POR
GND
Internal
Reset signal
GND
< 0.1V
Resetting period
Resetting period
R03DS0016EJ0100 Rev.1.00
2011.09.05
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R2A20162NS/SA/SP
New Product
( Vcc = +5V +/-10deg, GND = 0V, Ta = -30 to +85deg unless otherwise noted )
Symbol
Test Conditions
Limits
Min.
-
40
40
-
-
5
30
40
40
40
Ta=25deg, C
L
<100pF, V
AO
: 0.54.5V,
The time until the output becomes the final
value of 1/2 LSB.
-
Typ.
1.0
-
-
-
-
-
-
-
-
-
-
Max.
10
-
-
200
200
-
-
-
-
-
150
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AC Characteristics
Item
Clock frequency
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Data setup time
Data hold time
Load setup time
Load hold time
Load high pulse width
D/A output settling time
f
CLK
t
CKH
t
CKL
t
CR
t
CF
t
DCH
t
CHD
t
CHL
t
LDC
t
LDH
t
LDD
Timing Chart
t
CR
t
CKH
t
CF
CLK
t
CKL
DI
t
DCH
t
CHD
t
CHL
t
LDH
t
LDC
LD
t
LDD
D/A
output
(Note) Timing chart above is a schematic representation of the timing of each signal type.
CLK signal input is High or Low regardless, LD signal High input is enabled.
R03DS0016EJ0100 Rev.1.00
2011.09.05
Page 4 of 7
R2A20162NS/SA/SP
New Product
Digital Data Format
Last
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
First
MSB
D9
DAC data
Channel
Select data
Channel select data
D8
0
1
0
1
DAC data
D0
0
1
0
1
:
0
1
D1
0
0
1
1
:
1
1
D2
0
0
0
0
:
1
1
D3
0
0
0
0
:
1
1
D4
0
0
0
0
:
1
1
D5
0
0
0
0
:
1
1
D6
0
0
0
0
:
1
1
D7
0
0
0
0
:
1
1
DAC output
Vcc/256 x 1
Vcc/256 x 2
Vcc/256 x 3
Vcc/256 x 4
:
Vcc/256 x 255
Vcc
D9
0
0
1
1
Channel selection
Ao1 selected
Ao2 selected
Don’t care
Don’t care
Data timing chart ( Model )
DI
D9
D8
D7
D6
D5
D2
D1
D0
CLK
Whether CLK input is “H” or “L”,
High level input of LD signal is recognized.
LD
D/A
output
R03DS0016EJ0100 Rev.1.00
2011.09.05
Page 5 of 7
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