Preliminary
Datasheet
Specifications in this document are tentative and subject to change.
RL78/L12
RENESAS MCU
R01DS0157EJ0001
Rev.0.01
2012.02.20
Integrated LCD controller/driver, True Low Power Platform (as low as 75
µ
A/MHz, and 0.64
µ
A for RTC +
LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
1.
1.1
OUTLINE
Features
LCD Controller/Driver
•
Up to 35 seg x 8 com or 39 seg x 4 com
•
Supports capacitor split method, internal voltage
boost method and resistance division method
•
Supports waveform types A and B
•
Supports LCD contrast adjustment (18 steps)
•
Supports LCD blinking
Data Memory Access (DMA) Controller
•
Up to 2 fully programmable channels
•
Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
2
•
Up to 1
×
I C multi-master
•
Up to 2
×
CSI/SPI (7-, 8-bit)
•
Up to 1
×
UART (7-, 8-, 9-bit)
•
Up to 1
×
LIN
Extended-Function Timers
•
Multi-function 16-bit timers: Up to 8 channels
•
Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
•
Interval Timer: 12-bit, 1 channel
•
15 kHz watchdog timer: 1 channel (window function)
Rich Analog
•
ADC: Up to 10 channels, 10-bit resolution, 2.1
µs
conversion time
•
Supports 1.6 V
•
Internal voltage reference (1.45 V)
•
On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
•
Flash memory CRC calculation
•
RAM parity error check
•
RAM write protection
•
SFR write protection
•
Illegal memory access detection
•
Clock frequency detection
•
ADC self-test
General Purpose I/O
•
5V tolerant, high-current (up to 20 mA per pin)
•
Open-Drain, Internal Pull-up support
Operating Ambient Temperature
•
Standard:
−40
°C to +85 °C
Package Type and Pin Count
From 7mm x 7mm to 12mm x 12mm
QFP: 32, 44, 48, 52, 64
QFN: 64
Ultra-Low Power Technology
•
1.6 V to 5.5 V operation from a single supply
•
Stop (RAM retained): 0.23
µA,
(LVD enabled): 0.31
µA
•
Halt (RTC + LVD): 0.64
µA
•
Supports snooze
•
Operating: 75
µA/MHz
•
LCD operating current (Capacitor split method): 0.12
µA
•
LCD operating current (Internal voltage boost
method): 1.0
µA
16-bit RL78 CPU Core
•
Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
•
Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
•
CISC Architecture (Harvard) with 3-stage pipeline
•
Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
•
MAC: 16 x 16 to 32-bit result in 2 clock cycles
•
16-bit barrel shifter for shift & rotate in 1 clock cycle
•
1-wire on-chip debug function
Code Flash Memory
•
Density: 8 KB to 32 KB
•
Block size: 1 KB
•
On-chip single voltage flash memory with protection
from block erase/writing
•
Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
•
Data flash with background operation
•
Data flash size: 2 KB size
•
Erase cycles: 1 Million (typ.)
•
Erase/programming voltage: 1.8 V to 5.5 V
RAM
•
1 KB and 1.5 KB size options
•
Supports operands or instructions
•
Back-up retention in all modes
High-speed On-chip Oscillator
•
24 MHz with +/− 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (−20°C to 85°C) <target>
•
Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8
MHz, 4 MHz & 1 MHz
Reset and Supply Management
•
Power-on reset (POR) monitor/generator
•
Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 1 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
ROM, RAM capacities
Flash
ROM
32 KB
Data
flash
2 KB
1.5
KB
16 KB
2 KB
Note
RAM
32 pins
R5F10RBC
44 pins
R5F10RFC
RL78/L12
48 pins
R5F10RGC
52 pins
R5F10RJC
64 pins
R5F10RLC
1
KB
Note
R5F10RBA
R5F10RFA
R5F10RGA
R5F10RJA
R5F10RLA
8KB
2 KB
1
KB
Note
R5F10RB8
R5F10RF8
R5F10RG8
R5F10RJ8
−
Note
In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash
function is used.
Remark
The functions mounted depend on the product. See
1.6 Outline of Functions.
1.2
Ordering Information
•
Flash memory version (lead-free product)
Pin count
32 pins
44 pins
48 pins
Package
32-pin plastic LQFP (7
×
7)
44-pin plastic LQFP (10
×
10)
48-pin plastic LQFP
(fine pitch) (7
×
7)
52 pins
64 pins
52-pin plastic LQFP (10
×
10)
64-pin plastic WQFN (8
×
8)
64-pin plastic LQFP (fine pitch)
(10
×
10)
4-pin plastic LQFP (12
×
12)
R5F10RLAAFA, R5F10RLCAFA
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
R5F10RLAANB, R5F10RLCANB
R5F10RLAAFB, R5F10RLCAFB
Part Number
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 2 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.3.2
44-pin products
•
44-pin plastic LQFP (10
×
10)
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
33 32 31 30 29 28 27 26 25 24 23
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
P141/TI00/PCLBUZ1/SEG26
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/V
L3
V
L4
V
L2
V
L1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1.
For pin identification, see
1.4
redirection register (PIOR)
Pin Identification.
2.
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
P120/ANI17/SEG25
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 4 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.3.3
48-pin products
•
48-pin plastic LQFP (fine pitch) (7
×
7)
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
P10/SCK00/TI07/TO07/SEG28/(INTP1)
P140/TO00/PCLBUZ0/SEG27
P141/TI00/PCLBUZ1/SEG26
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P70/KR0/SEG16
P32/TI03/TO03/INTP4/KR1/SEG17
P31/INTP3/RTC1HZ/KR2/SEG18
P30/TI01/TO01/KR3/SEG19
P125/V
L3
V
L4
V
L2
V
L1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1.
For pin identification, see
1.4
redirection register (PIOR)
Pin Identification.
2.
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 5 of 73
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