dsPIC33EPXXX(GP/MC/MU)806/810/814
and PIC24EPXXX(GP/GU)810/814
16-Bit Microcontrollers and Digital Signal Controllers with
High-Speed PWM, USB and Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS
•
3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS
Timers/Output Compare/Input Capture
• 27 General Purpose Timers:
- Nine 16-bit and up to four 32-bit Timers/Counters
- 16 OC modules configurable as Timers/Counters
- Two 32-bit Quadrature Encoder Interface (QEI)
modules configurable as Timers/Counters
• 16 IC modules
• Peripheral Pin Select (PPS) to allow Function Remap
• Real-Time Clock and Calendar (RTCC) module
Core: 16-Bit dsPIC33E/PIC24E CPU
•
•
•
•
•
Code-Efficient (C and Assembly) architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL Plus Hardware Divide
32-Bit Multiply Support
Clock Management
•
•
•
•
•
2% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer
Fast Wake-up and Start-up
Communication Interfaces
• USB 2.0 OTG-Compliant Full-Speed Interface
• Four UART modules (15 Mbps)
- Supports LIN/J2602 protocols and IrDA
®
• Four 4-Wire SPI modules (15 Mbps)
• Two ECAN™ modules (1 Mbaud) CAN 2.0B Support
• Two I
2
C modules (up to 1 Mbaud) with SMBus Support
• Data Converter Interface (DCI) module with Support for
I
2
S and Audio Codecs
• PPS to allow Function Remap
• Parallel Master Port (PMP)
• Programmable Cyclic Redundancy Check (CRC)
Power Management
•
•
•
•
Low-Power Management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
1.0 mA/MHz Dynamic Current (typical)
60 µA I
PD
Current (typical)
High-Speed PWM
Up to Seven PWM Pairs with Independent Timing
Dead Time for Rising and Falling Edges
8.32 ns PWM Resolution
PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
•
•
•
•
Direct Memory Access (DMA)
• 15-Channel DMA with User-Selectable
Priority Arbitration
• UART, USB, SPI, ADC, ECAN™, IC, OC, Timers,
DCI/I
2
S, PMP
Input/Output
•
•
•
•
•
Sink/Source 10 mA on All Pins
5V Tolerant Pins
Selectable Open-Drain, Pull-ups and Pull-Downs
Up to 5 mA Overvoltage Clamp Current
External Interrupts on All I/O pins
Advanced Analog Features
• Two Independent ADC modules:
- One ADC configurable as 10-bit, 1.1 Msps with four
S&H or 12-bit, 500 ksps with one S&H
- One 10-bit ADC, 1.1 Msps with four S&H
- Eight S&H using both ADC 10-bit modules
- 24 analog channels (64-pin devices) up to 32 analog
channels (100/121/144-pin devices)
• Flexible and Independent ADC Trigger Sources
• Comparators:
- Up to three Analog Comparator modules
- Programmable references with 32 voltage points
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) Planned
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC) Planned
• Class B Safety Library, IEC 60730
Debugger Development Support
•
•
•
•
In-Circuit and In-Application Programming
Five Program and Three Complex Data Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
2009-2012 Microchip Technology Inc.
DS70616G-page 1
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
dsPIC33EPXXX(GP/MC/MU)806/810/814
and PIC24EPXXX(GP/GU)810/814
PRODUCT FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in
Table 1.
Their pinout diagrams appear on the following
pages.
TABLE 1:
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
CONTROLLER FAMILIES
Remappable Peripherals
Output Compare (with PWM)
Program Flash Memory
(Kbyte)
(1)
DMA Controller (Channels)
Analog Comparators/
Inputs Per Comparator
(7)
10-Bit/12-Bit ADC
(8)
External Interrupts
(6)
Motor Control PWM
(Channels)
(5)
Parallel Master Port
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
UART with IrDA
®
16-Bit Timer
(3,4)
Input Capture
CRC Generator
RAM (Kbyte)
(2)
Packages
ECAN™
QEI
dsPIC33EP256MU806
dsPIC33EP256MU810
64
100
QFN,
TQFP
TQFP
TQFP,
LQFP
QFN,
TQFP
QFN,
TQFP
TQFP
TQFP,
LQFP
TQFP
TQFP,
LQFP
QFN,
TQFP
TQFP
TQFP,L
QFP
DCI
SPI
Device
280
280
280
536
536
536
536
280
280
586
536
536
28
28
28
52
52
52
52
28
28
52
52
52
9
9
9
9
9
9
9
9
9
9
9
9
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
12
14
—
8
12
14
0
0
—
0
0
2
2
2
—
2
2
2
0
0
—
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
5
5
5
5
5
15
15
15
15
15
15
15
15
15
15
15
15
1
1
1
1
1
1
1
1
1
1
1
1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2 ADC,
24 ch
2 ADC,
32 ch
2 ADC,
32 ch
1
1
1
51
83
122
53
53
83
122
83
122
53
83
122
121 TFBGA
dsPIC33EP256MU814 144
dsPIC33EP512GP806
dsPIC33EP512MC806
dsPIC33EP512MU810
64
64
100
2 ADC,
—
24 ch
2 ADC,
—
24 ch
2 ADC,
32 ch
2 ADC,
32 ch
2 ADC,
32 ch
2 ADC,
32 ch
1
1
1
1
121 TFBGA
dsPIC33EP512MU814 144
PIC24EP256GU810
PIC24EP256GU814
PIC24EP512GP806
PIC24EP512GU810
PIC24EP512GU814
Note
1:
2:
3:
4:
5:
6:
7:
8:
100
121 TFBGA
144
64
100
2 ADC,
—
24 ch
2 ADC,
32 ch
2 ADC,
32 ch
1
1
121 TFBGA
144
Flash size is inclusive of 24 Kbytes of auxiliary Flash. Auxiliary Flash supports simultaneous code execution and self-erase/programming.
Refer to
Section 5. “Flash Programming”
(DS70609) in the
“dsPIC33E/PIC24E Family Reference Manual”.
RAM size is inclusive of 4 Kbytes of DMA RAM (DPSRAM) for all devices.
Up to eight of these timers can be combined into four 32-bit timers.
Eight out of nine timers are remappable.
PWM Faults and Sync signals are remappable.
Four out of five interrupts are remappable.
Comparator output is remappable.
The ADC2 module supports 10-bit mode only.
DS70616G-page 2
2009-2012 Microchip Technology Inc.
I/O Pins
RTCC
I
2
C™
Pins
USB
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Pin Diagrams
64-Pin QFN
= Pins are up to 5V tolerant
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AN29/PWM3H/PMD5/RP85/RE5
AN30/PWM4L/PMD6/RPI86/RE6
AN31/PWM4H/PMD7/RP87/RE7
C1IN3-/SCK2/PMA5/RP118/RG6
C1IN1-/SDI2/PMA4/RPI119/RG7
C2IN3-/SDO2/PMA3/RP120/RG8
MCLR
C2IN1-/PMA2/RPI121/RG9
V
SS
V
DD
AN5/C1IN1+/V
BUSON
/V
BUSST
/RPI37/RB5
AN4/C1IN2-/USBOEN/RPI36/RB4
AN3/C2IN1+/VPIO/RPI35/RB3
AN2/C2IN2-/VMIO/RPI34/RB2
PGEC3/AN1/V
REF
-/RPI33/RB1
PGED3/AN0/V
REF
+/RPI32/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN28/PWM3L/PMD4/RP84/RE4
AN27/PWM2H/PMD3/RPI83/RE3
AN26/PWM2L/PMD2/RP82/RE2
AN25/PWM1H/PMD1/RPI81/RE1
AN24/PWM1L/PMD0/RP80/RE0
V
CMPST
2/RP97/RF1
V
CMPST
1/RP96/RF0
V
DD
V
CAP
C3IN1+/V
CMPST
3/RP71/RD7
C3IN2-/RP70/RD6
PMRD/RP69/RD5
PMWR/RP68/RD4
PMBE/RP67/RD3
DPH/RP66/RD2
V
CPCON
/RP65/RD1
dsPIC33EP256MU806
PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14
PGED2/SOSCI/C3IN3-/RPI61/RC13
INT0/DMH/RP64/RD0
PMCS1/RPI75/RD11
ASCL1/PMCS2/RPI74/RD10
ASDA1/DPLN/RPI73/RD9
RTCC/DMLN/RPI72/RD8
V
SS
OSC2/CLKO/RC15
OSC1/RPI60/RC12
V
DD
D+/RG2
D-/RG3
V
USB3V3
V
BUS
USBID/RP99/RF3
Note 1:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See
Section 11.4 “Peripheral Pin Select”
for available peripherals and for information on limitations.
2:
Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See
Section 11.0
“I/O Ports”
for more information.
3:
The availability of I
2
C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is
made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See
Section 29.0
“Special Features”
for more information.
2009-2012 Microchip Technology Inc.
PGEC1/AN6/RPI38/RB6
PGED1/AN7/RCV/RPI39/RB7
AV
DD
AV
SS
AN8/PMA6/RPI40/RB8
AN9/PMA7//RPI41/RB9
TMS/AN10/CV
REF
/PMA13/RPI42/RB10
TDO/AN11/PMA12/RPI43/RB11
V
SS
V
DD
TCK/AN12/PMA11/RPI44/RB12
TDI/AN13/PMA10/RPI45/RB13
AN14/PMA1/RPI46/RB14
AN15/PMA0/RPI47/RB15
SDA2/PMA9/RP100/RF4
SCL2/PMA8/RP101/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DS70616G-page 3
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Pin Diagrams
64-Pin QFN
= Pins are up to 5V tolerant
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AN29/PWM3H/PMD5/RP85/RE5
AN30/PWM4L/PMD6/RPI86/RE6
AN31/PWM4H/PMD7/RP87/RE7
C1IN3-/SCK2/PMA5/RP118/RG6
C1IN1-/SDI2/PMA4/RPI119/RG7
C2IN3-/SDO2/PMA3/RP120/RG8
MCLR
C2IN1-/PMA2/RPI121/RG9
V
SS
V
DD
AN5/C1IN1+/RPI37/RB5
AN4/C1IN2-/RPI36/RB4
AN3/C2IN1+/RPI35/RB3
AN2/C2IN2-/RPI34/RB2
PGEC3/AN1/V
REF
-/RPI33/RB1
PGED3/AN0/V
REF
+/RPI32/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN28/PWM3L/PMD4/RP84/RE4
AN27/PWM2H/PMD3/RPI83/RE3
AN26/PWM2L/PMD2/RP82/RE2
AN25/PWM1H/PMD1/RPI81/RE1
AN24/PWM1L/PMD0/RP80/RE0
RP97/RF1
RP96/RF0
V
DD
V
CAP
C3IN1+/RP71/RD7
C3IN2-/RP70/RD6
PMRD/RP69/RD5
PMWR/RP68/RD4
PMBE/RP67/RD3
RP66/RD2
RP65/RD1
dsPIC33EP512MC806
PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14
PGED2/SOSCI/C3IN3-/RPI61/RC13
INT0/RP64/RD0
PMCS1/RPI75/RD11
ASCL1/PMCS2/RPI74/RD10
ASDA1/RPI73/RD9
RTCC/RPI72/RD8
V
SS
OSC2/CLKO/RC15
OSC1/RPI60/RC12
V
DD
SCLI/RG2
SDA1/RG3
RP102/RF6
RP98/RF2
RP99/RF3
Note 1:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See
Section 11.4 “Peripheral Pin Select”
for available peripherals and for information on limitations.
2:
Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See
Section 11.0
“I/O Ports”
for more information.
3:
The availability of I
2
C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is
made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See
Section 29.0
“Special Features”
for more information.
PGEC1/AN6/RPI38/RB6
PGED1/AN7/RPI39/RB7
AV
DD
AV
SS
AN8/PMA6/RPI40/RB8
AN9/PMA7//RPI41/RB9
TMS/AN10/CV
REF
/PMA13/RPI42/RB10
TDO/AN11/PMA12/RPI43/RB11
V
SS
V
DD
TCK/AN12/PMA11/RPI44/RB12
TDI/AN13/PMA10/RPI45/RB13
AN14/PMA1/RPI46/RB14
AN15/PMA0/RPI47/RB15
SDA2/PMA9/RP100/RF4
SCL2/PMA8/RP101/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DS70616G-page 4
2009-2012 Microchip Technology Inc.
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Pin Diagrams
64-Pin QFN
= Pins are up to 5V tolerant
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AN29/PMD5/RP85/RE5
AN30/PMD6/RPI86/RE6
AN31/PMD7/RP87/RE7
C1IN3-/SCK2/PMA5/RP118/RG6
C1IN1-/SDI2/PMA4/RPI119/RG7
C2IN3-/SDO2/PMA3/RP120/RG8
MCLR
C2IN1-/PMA2/RPI121/RG9
V
SS
V
DD
AN5/C1IN1+/RPI37/RB5
AN4/C1IN2-/RPI36/RB4
AN3/C2IN1+/RPI35/RB3
AN2/C2IN2-/RPI34/RB2
PGEC3/AN1/V
REF
-/RPI33/RB1
PGED3/AN0/V
REF
+/RPI32/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN28/PMD4/RP84/RE4
AN27/PMD3/RPI83/RE3
AN26/PMD2/RP82/RE2
AN25/PMD1/RPI81/RE1
AN24/PMD0/RP80/RE0
RP97/RF1
RP96/RF0
V
DD
V
CAP
C3IN1+/RP71/RD7
C3IN2-/RP70/RD6
PMRD/RP69/RD5
PMWR/RP68/RD4
PMBE/RP67/RD3
RP66/RD2
RP65/RD1
dsPIC33EP512GP806
PIC24EP512GP806
PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14
PGED2/SOSCI/C3IN3-/RPI61/RC13
INT0/RP64/RD0
PMCS1/RPI75/RD11
ASCL1/PMCS2/RPI74/RD10
ASDA1/RPI73/RD9
RTCC/RPI72/RD8
V
SS
OSC2/CLKO/RC15
OSC1/RPI60/RC12
V
DD
SCLI/RG2
SDA1/RG3
RP102/RF6
RP98/RF2
RP99/RF3
Note 1:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See
Section 11.4 “Peripheral Pin Select”
for available peripherals and for information on limitations.
2:
Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See
Section 11.0
“I/O Ports”
for more information.
3:
The availability of I
2
C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is
made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See
Section 29.0
“Special Features”
for more information.
2009-2012 Microchip Technology Inc.
PGEC1/AN6/RPI38/RB6
PGED1/AN7/RPI39/RB7
AV
DD
AV
SS
AN8/PMA6/RPI40/RB8
AN9/PMA7//RPI41/RB9
TMS/AN10/CV
REF
/PMA13/RPI42/RB10
TDO/AN11/PMA12/RPI43/RB11
V
SS
V
DD
TCK/AN12/PMA11/RPI44/RB12
TDI/AN13/PMA10/RPI45/RB13
AN14/PMA1/RPI46/RB14
AN15/PMA0/RPI47/RB15
SDA2/PMA9/RP100/RF4
SCL2/PMA8/RP101/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DS70616G-page 5
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