TS68020MR20 datasheet, PDF - EEWORLD Datasheet

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TS68020MR20: DescriptionHCMOS 32-bit Virtual Memory Microprocessor; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，45 Pages; ManufacturerAtmel (Microchip)

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TS68020MR20 Overview

HCMOS 32-bit Virtual Memory Microprocessor

TS68020MR20 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	PGA
package instruction	PGA, PGA114,13X13MOD
Contacts	114
Reach Compliance Code	unknow
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P114
JESD-609 code	e0
length	34.544 mm
low power mode	NO
Number of terminals	114
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA114,13X13MOD
Package shape	SQUARE
Package form	GRID ARRAY
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.75 mm
speed	20 MHz
Maximum slew rate	333 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	HCMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	34.544 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Features

•

Object Code Compatible with Earlier TS68000 Microprocessors

Addressing Mode Extensions for Enhanced Support of High Level Languages

New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics

Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth

Co-processor Interface to Companion 32-bit Peripherals: TS68881 and TS68882

Floating Point Co-processors

Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple

Instructions to be Executed Concurrently

High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits

Dynamic Bus Sizing Efficiently Supports 8-, 16-, 32-bit Memories and Peripherals

Full Support of Virtual Memory and Virtual Machine

Sixteen 32-bit General-purpose Data and Address Registers

Two 32-bit Supervisor Stack Pointers and 5 Special Purpose Control Registers

18 Addressing Modes and 7 Data Types

4-Gbyte Direct Addressing Range

Processor Speed: 16.67 MHz - 20 MHz - 25 MHz

Power Supply: 5.0 V

± 10%

HCMOS 32-bit

Virtual Memory

Microprocessor

TS68020

Description

The TS68020 is the first full 32-bit implementation of the TS68000 family of micropro-

cessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers

and data paths, 32-bit addresses, a rich instruction set, and versatile addressing

modes.

Screening/Quality

This product is manufactured in full compliance with either:

•

MIL-STD-883 (class B)

DESC 5962 - 860320

or according to Atmel standards

See “Ordering Information” on page 43.

Pin connection: see page 3.

R suffix

PGA 114

Ceramic Pin Grid Array

F suffix

CQFP 132

Ceramic Quad Flat Pack

Rev. 2115A–HIREL–07/02

Introduction

The TS68020 is a high-performance 32-bit microprocessor. It is the first microprocessor

to have evolved from a 16-bit machine to a full 32-bit machine that provides 32-bit

address and data buses as well as 32-bit internal structures. Many techniques were uti-

lized to improve performance and at the same time maintain compatibility with other

processors of the TS68000 Family. Among the improvements are new addressing

modes which better support high-level language structures, an expanded instruction set

which provides 32-bit operations for the limited cases not supported by the TS68000

and several new instructions which support new data types. For special-purpose appli-

cations when a general-purpose processor alone is not adequate, a co-processor

interface is provided.

The TS68020 is a high-performance microprocessor implemented in HCMOS, low

power, small geometry process. This process allows CMOS and HMOS (high density

NMOS) gates to be combined on the same device. CMOS structures are used where

speed and low power is required, and HMOS structures are used where minimum sili-

con area is desired. This technology enables the TS68020 to be very fast while

consuming less power (less than 1.5 watts) and still have a reasonably small die size. It

utilizes about 190.000 transistors, 103.000 of which are actually implemented. The

package is a pin-grid array (PGA) with 114 pins, arranged 13 pins on a side with a

depopulated center and 132 pins ceramic quad flat pack.

Figure 1 is a block diagram of the TS68020. The processor can be divided into two main

sections: the bus controller and the micromachine. This division reflects the autonomy

with which the sections operate.

Figure 1.

TS68020 Block Diagram

The bus controller consists of the address and data pads and multiplexers required to

support dynamic bus sizing, a macro bus controller which schedules the bus cycles on

the basis of priority with two state machines (one to control the bus cycles for operated

accesses and the other to control the bus cycles for instruction accesses), and the

instruction cache with its associated control.

TS68020

2115A–HIREL–07/02

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