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84129083X

Description
OT PLD, 35ns, TTL, CQCC28, LCC-28
CategoryProgrammable logic devices    Programmable logic   
File Size893KB,32 Pages
ManufacturerMonolithic Memories
Download Datasheet Parametric View All

84129083X Overview

OT PLD, 35ns, TTL, CQCC28, LCC-28

84129083X Parametric

Parameter NameAttribute value
MakerMonolithic Memories
package instructionLCC-28
Reach Compliance Codeunknown
maximum clock frequency15.4 MHz
JESD-30 codeS-CQCC-N28
length11.43 mm
Dedicated input times10
Number of I/O lines6
Number of terminals28
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize10 DEDICATED INPUTS, 6 I/O
Output functionMIXED
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Package shapeSQUARE
Package formCHIP CARRIER
Programmable logic typeOT PLD
propagation delay35 ns
Certification statusNot Qualified
Maximum seat height2.032 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyTTL
Temperature levelMILITARY
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
width11.43 mm
REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
C
Convert to military drawing format. Add vendor CAGE 01295.
Changes to table I. Delete subgroup 9 from final electrical test
parameters. Add case outline X. Added four devices 09 - 12.
Update part numbers for vendor CAGE number 01295. Correction on
page 18, terminal connections. Editorial changes throughout. Add
vendor CAGE numger 01295 as a supplier of the K package for
device types 01 through 08. Changes to pages 5 and 6 table I.
Changes to pages 10 and 11 terminal connections. Changes on
pages 21 - 28.
Correct figure 1 device types 02 and 04 for case outline X. Boilerplate
updated. ksr
Update drawing to current requirements. Editorial changes throughout.
ksr.
Update drawing to reflect current MIL-PRF-38535 requirements. – llb
87-07-06
M. A. Frye
D
88-05-06
M. A. Frye
E
F
G
04-08-06
09-11-30
17-09-27
Raymond Monnin
Charles F. Saffle
Charles F. Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
G
15
G
16
G
17
G
18
REV
SHEET
PREPARED BY
Greg Pitz
CHECKED BY
Charles Reusing
APPROVED BY
Michael Frye
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DRAWING APPROVAL DATE
84-08-24
REVISION LEVEL
G
19
G
20
G
21
G
1
G
22
G
2
G
23
G
3
G
24
G
4
G
25
G
5
G
26
G
6
G
27
G
7
G
28
G
8
G
29
G
9
G
30
G
10
G
11
G
12
G
13
G
14
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, MEMORY, DIGITAL,
BIPOLAR, PROGRAMMABLE LOGIC,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
1 OF 30
84129
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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