DATASHEET
Six Output Differential Buffer for PCIe Gen3
Recommended Application:
6 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB633 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB633 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB633 suitable for Express Card
applications.
Key Specifications:
•
Cycle-to-cycle jitter < 50 ps
•
Output-to-output skew < 50 ps
•
PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
9DB633
Features/Benefits:
•
OE# pins/Suitable for Express Card applications
•
PLL or bypass mode/PLL can dejitter incoming clock
•
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
•
Spread Spectrum Compatible/tracks spreading input
clock for low EMI
•
SMBus Interface/unused outputs can be disabled
Output Features:
•
6 - 0.7V current mode differential HCSL output pairs
OE1#
OE4#
DIF1
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
DIF4
PLL_BW
SMBDAT
SMBCLK
DIF(0,2,3,5)
CONTROL
LOGIC
IREF
IDT
®
Six Output Differential Buffer for PCIe Gen3
1668F—10/20/16
1
9DB633
Six Output Differential Buffer for PCIe Gen3
Datasheet
Pin Configuration
PLL_BW
SRC_IN
SRC_IN#
vOE1#
DIF_0
DIF_0#
VDD
GND
DIF_1
DIF_1#
DIF_2
DIF_2#
VDD
SMBDAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VD DA
GNDA
IREF
vOE4#
DIF_5
DIF_5#
VD D
GND
DIF_4
DIF_4#
DIF_3
DIF_3#
VD D
SMBCLK
Note:
Pins preceeded by ' v ' have internal
120K ohm pull down resistors
Power Distribution Table
Pin Number
VDD
GND
7, 13, 16, 22
8,21
13
8
N/A
27
28
27
Description
Differential Outputs
SMBus
IREF
Analog VDD & GND for PLL core
IDT
®
Six Output Differential Buffer for PCIe Gen3
9DB633
1668F—10/20/16
2
9DB633
Six Output Differential Buffer for PCIe Gen3
Datasheet
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN NAME
PLL_BW
SRC_IN
SRC_IN#
vOE1#
DIF_0
DIF_0#
VDD
GND
DIF_1
DIF_1#
DIF_2
DIF_2#
VDD
SMBDAT
SMBCLK
VDD
DIF_3#
DIF_3
DIF_4#
DIF_4
GND
VDD
DIF_5#
DIF_5
vOE4#
PIN TYPE
IN
IN
IN
IN
OUT
OUT
PWR
IN
OUT
OUT
OUT
OUT
PWR
I/O
IN
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power suppl y, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Power suppl y, nominal 3.3V
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power suppl y, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power suppl y, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
This pi n establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
27
28
IREF
GNDA
VDDA
OUT
PWR
PWR
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT
®
Six Output Differential Buffer for PCIe Gen3
1668F—10/20/16
3
9DB633
Six Output Differential Buffer for PCIe Gen3
Datasheet
CONDITIONS
UNITS NOTES
V
V
V
V
V
C
°C
V
°
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDA
VDD
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
MIN
TYP
MAX
4.6
4.6
V
DD
+0.5V
5.5V
GND-0.5
Except for SMBus interface
SMBus clock and data pins
-65
Human Body Model
2000
150
125
1,2
1,2
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
T
COM
T
IND
V
IH
V
IL
I
IN
Input Current
I
INP
F
ibyp
F
ipll
L
pin
C
IN
C
INDIF_IN
C
OUT
Clk Stabilization
Input SS Modulation
Frequency
OE# Latency
Tdrive_PD#
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
1
2
CONDITIONS
MIN
0
-40
2
GND - 0.3
-5
-200
10
33
1.5
1.5
TYP
MAX
70
85
V
DD
+ 0.3
0.8
5
200
110
110
7
5
2.7
6
1.8
UNITS NOTES
°C
°C
V
V
uA
uA
MHz
MHz
nH
pF
pF
pF
ms
1
1
1
1
1
1
2
2
1
1
1,4
1
1,2
Commmercial range
Industrial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, V
IN
= GND, V
IN
= VDD
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
V
DD
= 3.3 V, Bypass mode
V
DD
= 3.3 V, 100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of control inputs
Rise time of control inputs
Input Frequency
Pin Inductance
Capacitance
100.00
T
STAB
f
MODIN
30
33
kHz
1
t
LATOE#
t
DRVPD
t
F
t
R
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
V
DDSMB
t
RSMB
t
FSMB
f
MAXSMB
1
3
300
5
5
0.8
cycles
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1,3
1,3
1,2
1,2
1
1
1
1
1
1
1
1,5
2.1
@ I
PULLUP
@ V
OL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
4
2.7
V
DDSMB
0.4
5.5
1000
300
100
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
4
DIF_IN input
The differential input clock must be running for the SMBus to be active
IDT
®
Six Output Differential Buffer for PCIe Gen3
5
1668F—10/20/16
4
9DB633
Six Output Differential Buffer for PCIe Gen3
Datasheet
Electrical Characteristics - DIF_IN Clock Input Parameters
T
AMB
=T
COM
or T
IND
unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Input Crossover Voltage -
DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
V
CROSS
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Cross Over Voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential wavefrom
Differential Measurement
MIN
150
300
1
-5
45
0
TYP
375
MAX
900
UNITS NOTES
mV
mV
1
1
1,2
1
1
8
5
55
125
V/ns
uA
%
ps
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
T
A
= T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
Trf
CONDITIONS
MIN
TYP
MAX
Scope averaging on
0.6
2.5
4
9.5
20
Slew rate matching, Scope averaging on
Statistical measurement on single-ended signal
Voltage High
VHigh
660
740
850
1
using oscilloscope math function. (Scope averaging
mV
Voltage Low
VLow
-150
8
150
1
on)
Measurement on single ended signal using absolute
Vmax
760
1150
1
Max Voltage
mV
value. (Scope averaging off)
Vmin
-300
-3
1
Min Voltage
Vswing
Vswing
Scope averaging off
300
1506
mV
1, 2
Vcross_abs
Scope averaging off
250
378
550
mV
1, 5
Crossing Voltage (abs)
-Vcross
Crossing Voltage (var)
Scope averaging off
54
140
mV
1, 6
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
=
6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω (100 differential impedance).
Measured from differential waveform
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
3
4
2
UNITS NOTES
V/ns
1, 2, 3
%
1, 2, 4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
Electrical Characteristics - Current Consumption
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Operating Supply Current
Powerdown Current
1
CONDITIONS
MIN
TYP
134
MAX
150
N/A
N/A
UNITS NOTES
mA
mA
mA
1
1
1
I
DD3.3OP
I
DD3.3PD
I
DD3.3PDZ
All outputs active @100MHz, C
L
= Full load;
All diff pairs driven
All differential pairs tri-stated
Guaranteed by design and characterization, not 100% tested in production.
IDT
®
Six Output Differential Buffer for PCIe Gen3
1668F—10/20/16
5
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