End of Life. Last Available Purchase Date is 31-Dec-2014
Si9102
Vishay Siliconix
3-W High-Voltage Switchmode Regulator
DESCRIPTION
The Si9102 high-voltage switchmode regulator is a mono-
lithic BiC/DMOS integrated circuit which contains most of the
components necessary to implement a high-efficiency dc-to-
dc converter up to 3 watts. It can either be operated from
a low-voltage dc supply, or directly from a 10 to 120 V un-
regulated dc power source.
This device may be used with an appropriate transformer to
implement most single-ended isolated power converter
topologies (i.e., flyback and forward).
The Si9102 is available in both standard and lead (Pb)-free
14-pin plastic DIP and 20-pin PLCC packages which are
specified to operate over the industrial temperature range of
- 40 °C to 85 °C.
FEATURES
•
•
•
•
•
•
•
10 to 120 V Input Range
Current-Mode Control
On-chip 200 V, 7
MOSFET Switch
SHUTDOWN and RESET
High Efficiency Operation (> 80 %)
Internal Start-Up Circuit
Internal Oscillator (1 MHz)
FUNCTIONAL BLOCK DIAGRAM
OSC
IN
8 (11)
OSC
OUT
7 (10)
FB
14 (20)
COMP
13 (18)
DISCHARGE
9 (12)
Error
Amplifier
10 (14)
-
+
4 V (1 %)
Ref
Gen
2V
-
+
OSC
Clock (
1
/
2
f
OSC
)
Current-Mode
Comparator
R
Q
S
+
-
1.2 V
C/L
Comparator
3 (5)
DRAIN
- V
IN
(BODY)
V
REF
5 (8)
1 (2)
BIAS
6 (9)
Current
Sources
To
Internal
Circuits
4 (7)
V
CC
Undervoltage
Comparator
Q
R
SOURCE
V
CC
+V
IN
2 (3)
-
8.8 V
-
+
9.4 V
+
S
11 (16)
12 (17)
SHUTDOWN
RESET
Note: Figures in parenthesis represent pin numbers for 20-pin package.
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
www.vishay.com
1
End of Life. Last Available Purchase Date is 31-Dec-2014
Si9102
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltages Referenced to - V
IN
(V
CC
< + V
IN
+ 0.3 V)
V
CC
+V
IN
V
DS
I
D
(Peak) (Note: 300 µs pulse, 2 % duty cycle)
I
D
(rms)
Logic Inputs (RESET, SHUTDOWN, OSC IN)
Linear Inputs (FEEDBACK, SOURCE)
HV Pre-Regulator Input Current (continuous)
Storage Temperature
Operating Temperature
Junction Temperature (T
J
)
Power Dissipation (Package)
a
Thermal Impedance (
JA
)
14-Pin Plastic DIP (J Suffix)
b
20-Pin PLCC (N Suffix)
c
14-Pin Plastic DIP
20-Pin PLCC
Limit
15
120
200
2
250
- 0.3 V to V
CC
+ 0.3 V
- 0.3 to 7
3
- 65 to 125
- 40 to 85
150
750
1400
167
90
Unit
V
A
mA
V
mA
°C
mW
°C/W
Notes:
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 6 mW/°C above 25 °C.
c. Derate 11.2 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
Voltages Referenced to - V
IN
V
CC
R
OSC
Linear Inputs
+ V
IN
f
OSC
Digital Inputs
Limit
9.5 to 13.5
25 kto 1 M
0 to 7
10 to 120
40 kHzto 1 MHz
0 to V
CC
Unit
V
V
V
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
DISCHARGE = - V
IN
= 0 V
V
CC
= 10 V, + V
IN
= 48 V
R
BIAS
= 390 k, R
OSC
= 330 k
OSC IN = - V
IN
(OSC Disabled)
R
L
= 10 M
V
REF
= - V
IN
Limits
D Suffix - 40 to 85 °C
Temp
b
Room
Full
Room
Room
Full
Room
Room
Room
Room
Full
Min
d
3.92
3.86
15
70
Typ
c
4.0
30
100
0.5
3
100
200
10
200
Max
d
4.08
4.14
45
130
1.0
Parameter
Reference
Output Voltage
Output Impedance
e
Short Circuit Current
Temperature Stability
e
Oscillator
Maximum Frequency
e
Initial Accuracy
Voltage Stability
Temperature Coefficient
e
Symbol
Unit
V
R
Z
OUT
I
SREF
T
REF
f
MAX
f
OSC
f/f
T
OSC
V
k
µA
mV/°C
MHz
R
OSC
= 0
R
OSC
= 330 k
R
OSC
= 150 k
g
f/f
= f(13.5 V) - f(9.5 V)/f(9.5 V)
g
1
80
160
120
240
15
500
kHz
%
ppm/°C
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Document Number: 70001
S-70497-Rev. H, 19-Mar-07
End of Life. Last Available Purchase Date is 31-Dec-2014
Si9102
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
DISCHARGE = - V
IN
= 0 V
V
CC
= 10 V, + V
IN
= 48 V
R
BIAS
= 390 k, R
OSC
= 330 k
FB Tied to COMP
OSC IN = - V
IN
(OSC Disabled)
OSC IN = - V
IN
, V
FB
= 4 V,
OSC IN = - V
IN
(OSC Disabled)
Source (V
FB
= 3.4 V)
OSC IN = - V
IN
(OSC Disabled)
Sink (V
FB
= 4.5 V)
9.5 V
V
CC
13.5 V
R
L
= 100
from DRAIN to V
CC
V
FB
= 0 V
R
L
= 100
from DRAIN to V
CC
V
SOURCE
= 1.5 V, See Figure 1
I
IN
= 10 µA
V
CC
10 V
Pulse Width
300 µs, V
CC
= 7 V
I
PRE-REGULATOR
= 10 µA
R
L
= 100
from DRAIN to V
CC
See Detailed Description
Limits
D Suffix - 40 to 85 °C
Temp
b
Min
d
Typ
c
Max
d
Unit
Parameter
Error Amplifier
Feedback Input Voltage
Input BIAS Current
Open Loop Voltage Gain
e
Unity Gain Bandwidth
Output Current
Input OFFSET Voltage
Output Current
Power Supply Rejection
Current Limit
Threshold Voltage
Delay to Output
e
Pre-Regulator/Start-Up
Input Voltage
Input Leakage Current
Pre-Regulator Start-Up Current
V
CC
Pre-Regulator Turn-Off
Threshold Voltage
Undervoltage Lockout
V
REG
, - V
UVLO
Supply
Supply Current
Bias Current
Logic
SHUTDOWN Delay
e
SHUTDOWN Pulse Width
RESET Pulse Width
e
e
e
e
Symbol
V
FB
I
FB
A
VOL
BW
Z
OUT
I
OUT
V
OS
I
OUT
PSRR
Room
Room
Room
Room
Room
Room
Room
Room
Room
3.96
4.00
25
4.04
500
V
nA
dB
MHz
60
0.7
80
1
1000
- 2.0
± 15
2000
- 1.4
± 40
Dynamic Output Impedance
mA
mV
mA
dB
0.12
50
0.15
70
V
SOURCE
t
d
Room
Room
1.0
1.2
100
1.4
200
V
ns
+ V
IN
+ I
IN
I
START
V
REG
V
UVLO
V
DELTA
I
CC
I
BIAS
t
SD
t
SW
t
RW
t
LW
V
IL
V
IH
I
IH
I
IL
V
BR(DSS)
r
DS(on)
I
DSS
Room
Room
Room
Room
Room
Room
Room
Room
8
7.8
7.0
0.3
0.45
10
15
9.4
8.8
0.6
0.6
15
50
50
50
25
120
10
V
µA
mA
9.7
9.2
V
1.0
20
100
mA
µA
V
SOURCE
= - V
IN
, See Figure 2
Room
Room
Room
Room
Room
Room
8.0
Latching Pulse Width
e
SHUTDOWN and RESET Low
Input Low Voltage
Input High Voltage
Input Current Input Voltage High
Input Current Input Voltage Low
MOSFET Switch
Breakdown Voltage
Drain-Source On Resistance
f
Drain Off Leakage Current
See Figure 3
ns
2.0
1
- 35
200
- 25
220
7
5
10
5
V
µA
V
IN
= 10 V
V
IN
= 0 V
I
DRAIN
= 100 µA
I
DRAIN
= 100 mA
V
DRAIN
= 100 V
Room
Room
Full
Room
Room
V
µA
Room
35
pF
Drain Capacitance
C
DS
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. Temperature coefficient of r
DS(on)
is 0.75 % per °C, typical.
g. C
STRAY
Pin 8 =
5 pF.
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
www.vishay.com
3
End of Life. Last Available Purchase Date is 31-Dec-2014
Si9102
Vishay Siliconix
TIMING WAVEFORMS
1.5 V -
SOURCE
0
V
CC
-
DRAIN
0
50 %
t
d
t
r
≤
10 ns
V
CC
SHUTDOWN
0 -
V
CC
-
DRAIN
0
50 %
t
SD
t
f
≤
10 ns
10 %
10 %
Figure 1.
Figure 2.
t
SW
V
CC
SHUTDOWN
0 -
V
CC
RESET
0 -
50 %
50 %
t
RW
50 %
50 %
t
LW
50 %
t
r
, t
f
≤
10 ns
Figure 3.
TYPICAL CHARACTERISTICS
140
V
CC
= - V
IN
120
100
+V IN (V)
80
60
40
20
0
10
15
+I
IN
(mA)
20
f OUT (Hz)
1M
100 k
10 k
10 k
100 k
r
OSC
- Oscillator Resistance (Ω)
1M
Figure 4. + V
IN
vs. + I
IN
at Start-Up
Figure 5. Output Switching Frequency
vs. Oscillator Resistance
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Document Number: 70001
S-70497-Rev. H, 19-Mar-07
End of Life. Last Available Purchase Date is 31-Dec-2014
Si9102
Vishay Siliconix
PIN CONFIGURATIONS
PDIP-14
1
2
3
4
5
6
7
Top View
14
13
12
11
10
9
8
PIN DESCRIPTION
Function
BIAS
+ V
IN
DRAIN
SOURCE
- V
IN
V
CC
OSC OUT
OSC IN
DISCHARGE
V
REF
Pin
14-Pin DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20-Pin PLCC*
2
3
5
7
8
9
10
11
12
14
16
17
18
20
PLCC-20
3
2
1
20 19
SHUTDOWN
RESET
COMP
FB
4
5
6
7
8
18
17
16
15
14
*Pins 1, 4, 6, 13, 15, and 19 = N/C
ORDERING INFORMATION
Standard
Part Number
Si9102DJ02
Si9102DN02
Lead (Pb)-free
Part Number
Si9102DJ02-E3
Si9102DN02-E3
- 40 to 85 °C
PLCC-20
Temperature
Range
Package
PDIP-14
9
10 11 12 13
Top View
Si9102DN02-T1 Si9102DN02-T1-E3
(With Tape
(With Tape
and Reel)
and Reel)
DETAIL DESCRIPTION
Pre-Regulator/Start-Up Section
Due to the low quiescent current requirement of the Si9102
control circuitry, bias power can be supplied from the unreg-
ulated input power source, from an external regulated low-
voltage supply, or from an auxiliary "bootstrap" winding on
the output inductor or transformer.
When power is first applied during start-up, + V
IN
will draw a
constant current. The magnitude of this current is determined
by a high-voltage depletion MOSFET device which is con-
nected between + V
IN
and V
CC
. This start-up circuitry pro-
vides initial power to the IC by charging an external bypass
capacitance connected to the V
CC
pin. The constant current
is disabled when V
CC
exceeds 9.4 V. If V
CC
is not forced to
exceed the 9.4 V threshold, then V
CC
will be regulated to a
nominal value of 9.4 V by the pre-regulator circuit.
As the supply voltage rises toward the normal operating con-
ditions, an internal undervoltage (UV) lockout circuit keeps
the output MOSFET disabled until V
CC
exceeds the under-
voltage lockout threshold (typically 8.8 V). This guarantees
that the control logic will be functioning properly and that suf-
ficient gate drive voltage is available before the MOSFET
turns on. The design of the IC is such that the undervoltage
lockout threshold will not exceed the pre-regulator turn-off
voltage. Power dissipation can be minimized by providing an
external power source to V
CC
such that the constant current
source is always disabled.
Note:
During start-up or when V
CC
drops below 9.4 V the
start-up circuit is capable of sourcing up to 20 mA. This may
lead to a high level of power dissipation in the IC (for a 48 V
input, approximately 1 W). Excessive start-up time caused
by external loading of the V
CC
supply can result in device
damage. Figure 4 gives the typical pre-regulator current at
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