BU-6174X/6184X/6186X
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
(ENHANCED MINI-ACE)
DESCRIPTION
The Enhanced Mini-ACE family of
MIL-STD-1553 terminals provide
complete interfaces between a
host processor and a 1553 bus.
These terminals integrate dual
transceiver, protocol logic, and
4K words or 64K words of RAM.
With a 1.0 inch square package,
the Enhanced Mini-ACE is nearly
100% footprint and software com-
patibile with the previous genera-
tion Mini-ACE (Plus) terminals, and
is software compatibile with the
older ACE series.
The Enhanced Mini-ACE is pow-
ered by a choice 5V, or 5V/3.3V
(3.3V logic). Multiprotocol support
of
MIL-STD-1553A/B
and
STANAG 3838, including versions
incorporating McAir compatible
transmitters, is provided. There is a
choice of 10, 12, 16, or 20 Mhz
clocks. The BC/RT/MT versions
with 64K words of RAM include
built-in RAM parity checking.
BC features include a built-in mes-
sage sequence control engine,
with a set of 20 instructions. This
provides an autonomous means of
implementing multi-frame mes-
sage scheduling, message retry
schemes, data double buffering,
asynchronous message insertion,
and reporting to the host CPU. The
Enhanced Mini-ACE incorporates
a fully autonomous built-in self-test,
which provides comprehensive
testing of the internal protocol logic
and/or RAM.
The Enhanced Mini-ACE RT offers
the same choices of subaddress
buffering as the ACE and Mini-ACE
(Plus), along with a global circular
buffering option, 50% rollover inter-
rupt for circular buffers, an interrupt
status queue, and an "Auto-boot"
option to support MIL-STD-1760.
The Enhanced Mini-ACE terminals
provide the same flexibility in host
interface configurations as the
ACE/Mini-ACE, along with a reduc-
tion in the host processor's worst
case holdoff time.
FEATURES
•
FULLY INTEGRATED 1553A/B NOTICE 2,
•
COMPATIBLE WITH MINI-ACE (PLUS)
AND ACE GENERATIONS
MCAIR, STANAG 3838 INTERFACE TERMINAL
•
CHOICE OF :
•
RT OR BC/RT/MT IN SAME FOOTPRINT
•
RT OR BC/RT/MT WITH 4K RAM
•
BC/RT/MT WITH 64K RAM, WITH RAM PARITY
•
CHOICE OF 5V OR 3.3V LOGIC
•
5V TRANSCEIVER WITH 1760 AND
MCAIR COMPATIBLE OPTIONS
•
COMPREHENSIVE BUILT-IN SELF-TEST
•
FLEXIBLE PROCESSOR/MEMORY
INTERFACE, WITH REDUCED HOST WAIT TIME
•
CHOICE OF 12, 12, 18, OR 20 MHZ CLOCK
•
HIGHLY AUTONOMOUS BC WITH
BUILT-IN MESSAGE SEQUENCE CONTROL:
•
FRAME SCHEDULING
•
BRANCHING
•
ASYNCHRONOUS MESSAGE INSERTION
•
GENEERAL PURPOSE QUEUE
•
USER-DEFINED INTERRUPTS
•
ADVANCED RT FUNCTIONS
INTERRPTS
•
GLOBAL CIRCULAR BUFFERING
•
INTERRUPT STATUS QUEUE
•
50% CIRCULAR BUFFER ROLLOVER
TX/RX_A
SHARED
RAM
CH. A
TRANSCEIVER
A
DATA
BUFFERS
PROCESSOR
DATA BUS
*
TX/RX_A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
D15-D0
TX/RX_B
ADDRESS BUS
ADDRESS
BUFFERS
A15-A0
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
TX/RX_B
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD
MISCELLANEOUS
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ENHANCED MINI-ACE BLOCK DIAGRAM
©
2000 Data Device Corporation
TABLE 1. EHANCED MINI-ACE SERIES SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
!
Logic +5V or +3.3V
!
RAM +5V
!
Transceiver +5V (Note 11)
Logic
!
Voltage Input Range for +5V
Logic (BU-61XX5)
!
Voltage Input Range for +3.3V
Logic (BU-61XX3/4)
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
MIN
TYP
MAX
UNITS
TABLE 1. EHANCED MINI-ACE SERIES SPECIFICATIONS (Cont’d)
PARAMETER
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
!
+5V (RAM for 61864(5),
Logic for BU-61XX5) (Note 11)
!
+3.3V (Logic for BU-61XX3/4)
(Note 11)
!
+5V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
!
BU-61865
• +5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61864
• +5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
!
BU-61845. BU-61745
• +5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61743
• +5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
POWER DISSIPATION
Total Hybrid
!
BU-61865
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61864
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61845, BU-61745
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61863, BU-61743
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
6.0
7.0
6.0
6.0
V
V
V
V
V
4.5
3.0
4.75
5.0
3.3
5.0
5.5
3.6
5.5
V
V
V
2.5
5
0.200
0.860
10
kΩ
pF
Vp-p
Vpeak
160
260
360
560
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
TRANSMITTER
Differential Output Voltage
!
Direct Coupled Across 35
Ω,
6
Measured on Bus
!
Transformer Coupled Across
70
Ω,
Measured on Bus
18
(BU-61XXXXX-XX0,
20
BU-61XXXXX-XX2) (Note 13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer -250
Coupled Across 70 ohms
Rise/Fall Time
100
(BU-61XXXX3,
200
BU-61XXXX4)
LOGIC
V
IH
All signals except CLK_IN
2.1
CLK_IN
0.8•Vcc
V
IL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
0.4
CLK_IN
1.0
I
IH,
I
IL
All signals except CLK_IN
I
IH
(Vcc=5.5V, V
IN
=Vcc)
-10
I
IH
(Vcc=5.5V, V
IN
=2.7V)
-350
I
IL
(Vcc=3.6V, V
IN
=Vcc)
-10
I
IH
(Vcc=3.6V, V
IH
=2.7V)
-350
I
IL
(Vcc=5.5V, V
IH
=0.4V)
-350
I
IL
(Vcc=3.6V, V
IH
=0.4V)
-350
CLK_IN
I
IH
-10
I
IL
-10
V
OH
(Vcc=4.5V, V
IH
=2.7V,
2.4
V
IL
=0.2V, I
OH
=max)
V
OH
(Vcc=3.0V, V
IH
=2.7V,
2.4
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
V
OL
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
I
OL
3.4
I
OH
C
I
(Input Capacitance)
C
IO
(Bi-directional signal input
capacitance)
7
9
Vp-p
100
200
300
500
40
20
22
27
27
10
250
Vp-p
Vp-p
M
V
P
-
P
mV
peak
140
240
340
540
150
250
300
300
nsec
nsec
80
180
280
480
40
V
V
0.7
0.2•Vcc
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
V
0.4
0.4
V
V
mA
mA
pF
pF
0.88
1.08
1.28
1.68
0.69
0.89
1.09
1.49
0.77
0.97
1.17
1.57
0.58
0.78
0.98
1.38
0.22
0.42
0.62
1.02
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
10
-50
10
-33
-50
-33
10
10
-3.4
50
50
2
TABLE 1. EHANCED MINI-ACE SERIES SPECIFICATIONS (Cont’d)
PARAMETER
CLOCK INPUT
Frequency
!
Nominal Value
• Default Mode
• Option
• Option
• Option
!
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
!
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
!
Duty Cycle
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of Next Message
for (Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
MIN
TYP
MAX UNITS
NOTES:
Notes 1 through 6 are applicable to the Receiver Differential
Resistance and Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
Impedance parameters are specified directly between pins TX/RX
A(B) and
TX / RX A(B)
of the Enhanced Mini-ACE hybrid.
It is assumed that all power and ground inputs to the hybrid are
connected.
The specifications are applicable for both unpowered and powered
conditions.
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
Assumes a common mode voltage within the frequency range of
dc to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to
hybrid ground. Transformer must be a DDC recommended trans-
former or other transformer that provides an equivalent minimum
CMRR.
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened to 65,535 ms - message time, in
increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6
clock cycles. Since there are 7 internal transfers during SOM, and
5 during EOM, this could theoretically lengthen the intermessage
gap by up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock,
6.0 µs with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs
with a 20 MHz clock.
For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 µs at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
16.0
12.0
10.0
20.0
-0.01
-0.10
0.001
-0.01
40
2.5
0.01
0.1
0.001
0.01
60
MHz
MHz
MHz
MHz
%
%
%
%
%
µs
(2)
(3)
(4)
(5)
(6)
9.5
10.0
to
10.5
17.5
21.5
49.5
127
4
18.5
22.5
50.5
129.5
19.5
23.5
51.5
131
7
µs
(7)
µs
µs
µs
µs
µs
µs
µs
(8)
BC/RT/MT Response Timeout (Note 10)
!
18.5 nominal
!
22.5 nominal
!
50.5 nominal
!
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (θ
JC
)
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Size
660.5
-55
-65
20
150
150
+300
°C/W
°C
°C
°C
(9)
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
Weight
0.6
(17)
in.
(mm)
oz
(g)
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) External 10 pF Tantalum and 0.1 µF capacitors should be located
as close as possible to Pins 20 and 72, and a 0.1 µF at pin 37. For
BU-61864 and BU-61865, there should also be a 0.1 µF at pin 26.
(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub
connection.
3
INTRODUCTION
The BU-61743/61745 RT, and BU-61843/61845/61864/61865
BC/RT/MT Enhanced Mini-ACE family of MIL-STD-1553 termi-
nals comprise a complete integrated interface between a host
processor and a MIL-STD-1553 bus. All members of the
Enhanced Mini-ACE family are packaged in the same 1.0 square
inch flatpack package. The Enhanced Mini-ACE hybrids are
nearly 100% footprint and software compatible with the previous
generation Mini-ACE and Mini-ACE Plus terminals, and are soft-
ware compatibility with the original ACE series.
The Enhanced Mini-ACE provides complete multiprotocol sup-
port of MIL-STD-1553A/B/McAir and STANAG 3838. All versions
integrate dual transceiver; along with protocol, host interface,
memory management logic; and a minimum of 4K words of
RAM. In addition, the BU-61864 and BU-61865 BC/RT/MT ter-
minals include 64K words of internal RAM, with built-in parity
checking.
The Enhanced Mini-ACEs include a 5V, voltage source trans-
ceiver for improved line driving capability, with options for MIL-
STD-1760 and McAir compatibility. As a means of reducing
power consumption, there are versions for which the logic is
powered by 3.3V, rather than 5V. To provide further flexibility, the
Enhanced Mini-ACE may operate with a choice of 10, 12, 16, or
20 MHz clock inputs.
One of the new salient features of the Enhanced Mini-ACE is its
Enhanced bus controller architecture. The Enhanced BC's high-
ly autonomous message sequence control engine provides a
means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
A second major new feature of the Enhanced Mini-ACE is the
incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the internal RAM. Since
the self-tests are fully autonomous, they eliminate the need for
the host to write and read stimulus and response vectors.
The Enhanced Mini-ACE RT offers the same choices of single,
double, and circular buffering for individual subaddresses as
ACE and Mini-ACE (Plus). New enhancements to the RT archi-
tecture include a global circular buffering option for multiple (or
all) receive subaddresses, a 50% rollover interrupt for circular
buffers, an interrupt status queue for logging up to 32 interrupt
events, and an option to automatically initialize to RT mode with
the Busy bit set. The interrupt status queue and 50% rollover
interrupt features are also included as improvements to the
Enhanced Mini-ACE's Monitor architecture.
To minimize board space and "glue" logic, the Enhanced Mini-
ACE terminals provide the same wide choice of host interface
configurations as the ACE and Mini-ACE (Plus). This includes
support of interfaces to 16-bit or 8-bit processors, memory or
port type interfaces, and multiplexed or non-multiplexed
address/data buses. In addition, with respect to ACE/Mini-ACE
(Plus), the worst case processor wait time has been significant-
ly reduced. For example, assuming a 16 MHz clock, this time has
been reduced from 2.8
µs
to 632 ns for read accesses, and to
570 ns for write accesses.
The Enhanced Mini-ACE series terminals operate over the full
military temperature range of -55 to +125°C. Available screened
to MIL-PRF-38534C, the terminals are ideal for military and
industrial processor-to-1553 applications.
TRANSCEIVERS
The transceivers in the Enhanced Mini-ACE series terminals are
fully monolithic, requiring only a +5 volt power input. The trans-
mitters are voltage sources, which provide improved line driving
capability over current sources. This serves to improve perfor-
mance on long buses with many taps. The transmitters also offer
an option which satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +5V-only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides the
advantage of a higher terminal input impedance than is possible
for a 15 volt or 12 volt transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553 val-
idation test. This characteristic allows for longer cable lengths
between a system connector and the isolation transformers of an
embedded 1553 terminal.
To provide compatibility to McAir specs, the Enhanced Mini-
ACEs are available with an option for transmitters with increased
rise and fall times.
Additionally, for MIL-STD-1760 applications, the Enhanced Mini-
ACE provides an option for a minimum stub voltage level of 20
volts peak-to-peak, transformer coupled.
The receiver sections of the Enhanced Mini-ACE are fully com-
pliant with MIL-STD-1553B Notice 2 in terms of front end over-
voltage protection, threshold, common mode rejection, and word
error rate.
REGISTER AND MEMORY ADDRESSING
The software interface of the Enhanced Mini-ACE to the host
processor consists of 24 internal operational registers for normal
operation, an additional 24 test registers, plus 64K words of
shared memory address space. The Enhanced Mini-ACE's 4K X
16 or 64K X 17 internal RAM resides in this address space.
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1F). The next 32
locations (20-3F) should be reserved, since many of these are
used for factory test.
4
INTERNAL REGISTERS
The address mapping for the Enhanced Mini-ACE registers is illustrated in TABLE 2:
TABLE 2. ADDRESS MAPPING
ADDRESS LINES
A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0 Interrupt Mask Register #1 (RD/WR)
1 Configuration Register #1 (RD/WR)
0 Configuration Register #2 (RD/WR)
1 Start/Reset Register (WR)
Non-Enhanced BC/RT Command Stack Pointer /
1 Enhanced BC Instruction List Pointer Register
(RD)
0
BC Control Word /
RT Subaddress Control Word Register (RD/WR)
REGISTER
DESCRIPTION/ACCESSIBILITY
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
1 Time Tag Register (RD/WR)
0 Interrupt Status Register #1 (RD)
1 Configuration Register #3 (RD/WR)
0 Configuration Register #4 (RD/WR)
1 Configuration Register #5 (RD/WR)
0 RT / Monitor Data Stack Address Register (RD)
1 BC Frame Time Remaining Register (RD)
0
BC Time Remaining to Next Message Register
(RD)
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
Non-Enhanced BC Frame Time / Enhanced BC
1 Initial Instruction Pointer / RT Last Command /
MT Trigger Word Register(RD/WR)
0 RT Status Word Register (RD)
1 RT BIT Word Register (RD)
0 Test Mode Register 0
1 Test Mode Register 1
0 Test Mode Register 2
0 Test Mode Register 3
0 Test Mode Register 4
1 Test Mode Register 5
0 Test Mode Register 6
1 Test Mode Register 7
0 Configuration Register #6 (RD/WR)
1 Configuration Register #7 (RD/WR)
0 RESERVED
1 BC Condition Code Register (RD)
1 BC General Purpose Flag Register (WR)
0 BIT Test Status Register (RD)
1 Interrupt Mask Register #2 (RD/WR)
0 Interrupt Status Register #2 (RD)
BC General Purpose Queue Pointer /
1 RT-MT Interrupt Status Queue Pointer Register
(RD/WR)
5
FPGA/CPLD
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