STL21N65M5
N-channel 650 V, 0.175
Ω
17 A ultra low gate charge MDmesh™ V
,
Power MOSFET in PowerFLAT™ 8x8 HV package
Datasheet — production data
Features
Order code
STL21N65M5
V
DSS
@
T
Jmax
710 V
R
DS(on)
max
< 0.190
Ω
I
D
17 A
(1)
1. The value is rated according to R
thj-case
■
■
■
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
Applications
■
Switching applications
Figure 1.
Internal schematic diagram
Description
This device is an N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary
vertical process technology, which is combined
with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low on-
resistance, which is unmatched among silicon-
based Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
Table 1.
Device summary
Marking
21N65M5
Package
PowerFLAT™ 8x8 HV
Packaging
Tape and reel
Order code
STL21N65M5
May 2012
This is information on a product in full production.
Doc ID 17438 Rev 5
1/16
www.st.com
16
Contents
STL21N65M5
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
4
5
6
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
Doc ID 17438 Rev 5
STL21N65M5
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D (1)
I
D (1)
I
D(3)
I
D(3)
P
TOT (3)
P
TOT(1)
I
AR
E
AS
dv/dt
(4)
T
stg
T
j
Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Value
650
± 25
17
11
68
2.7
1.7
10.8
3
125
5
400
15
- 55 to 150
150
Unit
V
V
A
A
A
A
A
A
W
W
A
mJ
V/ns
°C
°C
I
DM (1),(2)
Drain current (pulsed)
Drain current (continuous) at T
amb
= 25 °C
Drain current (continuous) at T
amb
= 100 °C
I
DM(2),(3)
Drain current (pulsed)
Total dissipation at T
amb
= 25 °C
Total dissipation at T
C
= 25 °C
Avalanche current, repetitive or not-
repetitive (pulse width limited by T
j
max)
Single pulse avalanche energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Peak diode recovery voltage slope
Storage temperature
Max. operating junction temperature
1. The value is rated according to R
thj-case.
2. Pulse width limited by safe operating area.
3. When mounted on FR-4 board of inch², 2oz Cu.
4. I
SD
≤
17 A, di/dt
≤
400 A/µs, V
Peak
< V
(BR)DSS
, V
DD
= 400 V.
Table 3.
Symbol
R
thj-case
Thermal data
Parameter
Thermal resistance junction-case max
Value
1
45
Unit
°C/W
°C/W
R
thj-amb(1)
Thermal resistance junction-amb max
1. When mounted on 1inch² FR-4 board, 2 oz Cu.
Doc ID 17438 Rev 5
3/16
Electrical characteristics
STL21N65M5
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On /off states
Parameter
Drain-source
breakdown voltage
Test conditions
I
D
= 1 mA, V
GS
= 0
Min.
650
1
100
±100
3
4
0.175
5
0.190
Typ.
Max.
Unit
V
µA
µA
nA
V
Ω
Zero gate voltage
V
DS
= 650 V
drain current (V
GS
= 0) V
DS
= 650 V, T
C
=125 °C
Gate-body leakage
current (V
DS
= 0)
V
GS
= ± 25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source
on-resistance
V
GS
= 10 V, I
D
= 8.5 A
Table 5.
Symbol
C
iss
C
oss
C
rss
(1)
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent
capacitance time
related
Equivalent
capacitance energy
related
Intrinsic gate
resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 0 to 520 V, V
GS
= 0
-
44
-
pF
Test conditions
Min.
Typ.
1950
46
3
Max.
Unit
pF
pF
pF
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0
-
-
C
o(tr)
-
133
-
pF
C
o(er)(2)
R
G
Q
g
Q
gs
Q
gd
f = 1 MHz open drain
V
DD
= 520 V, I
D
= 8.5 A,
V
GS
= 10 V
(see
Figure 16)
-
2.5
44
12
17
-
Ω
nC
nC
nC
-
-
1. C
oss eq.
time related is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
2. C
oss eq.
energy related is defined as a constant equivalent capacitance giving the same stored energy as
C
oss
when V
DS
increases from 0 to 80% V
DSS
4/16
Doc ID 17438 Rev 5
STL21N65M5
Electrical characteristics
Table 6.
Symbol
t
d(off)
t
r
t
c
t
f
Switching times
Parameter
Turn-off delay time
Rise time
Cross time
Fall time
Test conditions
V
DD
= 400 V, I
D
= 11 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
(see
Figure 17),
(see
Figure 20)
Min.
Typ.
37
10
24
12
Max
Unit
ns
ns
ns
ns
-
-
Table 7.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 17 A, V
GS
= 0
I
SD
= 17 A, di/dt = 100 A/µs
V
DD
= 100 V (see
Figure 17)
I
SD
= 17 A, di/dt = 100 A/µs
V
DD
= 100 V, T
j
= 150 °C
(see
Figure 17)
Test conditions
Min.
-
-
-
294
4
28
340
5
29
Typ.
Max. Unit
17
68
1.5
A
A
V
ns
µC
A
ns
µC
A
V
SD (2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
-
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Doc ID 17438 Rev 5
5/16
京公网安备 11010802033920号
EEWORLD
