Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers
DESCRIPTION
The DG528 is an 8-channel single-ended analog multiplexer
designed to connect one of eight inputs to a common output
as determined by a 3-bit binary address (A
0
, A
1
, A
2
). DG529,
a 4-channel dual analog multiplexer, is designed to connect
one of four differential inputs to a common differential output
as determined by its 2-bit binary address (A
0
, A
1
) logic.
These analog multiplexers have on-chip address and control
latches to simplify design in microprocessor based applica-
tions. Break-before-make switching action protects against
momentary shorting of the input signals. The DG528/529 are
built on the improved PLUS-40 CMOS process. A buried
layer prevents latchup.
The on chip TTL-compatible address latches simplify digital
interface design and reduce board space in data acquisition
systems, process controls, avionics, and ATE.
FEATURES
• Low R
DS(on)
: 270
• 44 V Power Supply Rating
• On-Board Address Latches
• Break-Before-Make
• Low Leakage - I
D(on)
: 30 pA
BENEFITS
• Improved System Accuracy
• Microporcessor Bus Compatible
• Easily Interfaced
• Reduced Crosstalk
APPLICATIONS
• Data Acquisition Systems
• Automatic Test Equipment
• Avionics and Military Systems
• Medical Instrumentation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG528
DG528
DG529
Dual-In-Line
A0
WR
A
0
EN
V-
S
1
S
2
S
3
S
4
D
1
2
3
4
5
6
7
8
9
1
Latches
Decoders/Drivers
18
17
16
15
14
13
12
11
0
RS
A
1
A
2
GND
V+
S
5
S
6
S
7
S
8
9
S4
EN
V
±
S
1
S
2
S
3
4
5
6
7
8
PLCC
WR
A1
NC
RS
WR
A
0
EN
Latches
Decoders/Drivers
18 A
2
17 GND
16 V+
15 S
5
14 S
6
S
3a
10 11 12 13
S8
NC
S7
D
S
4a
D
a
V-
S
1a
S
2a
1
2
3
4
5
6
7
8
9
Dual-In-Line
18
17
Latches
Decoders/Drivers
16
15
14
13
12
11
10
RS
A
1
GND
V+
S
1b
S
2b
S
3b
S
4b
D
b
3
2
1
20 19
Top View
Top View
Top View
Document Number: 70068
S11-1029–Rev. D, 23-May-11
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG528, DG529
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE - DG528
8-Channel Single-Ended Multiplexer
A
2
A
1
A
0
EN
WR
RS
On Switch
Maintains previous
switch condition
None (latches cleared)
None
1
2
3
4
5
6
7
8
A
0
Latching
X
X
1
X
Reset
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
0
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X
X
0
1
0
1
X
0
1
1
1
1
X
0
0
0
0
0
0
1
1
1
1
1
None (latches cleared)
None
1
2
3
4
Transparent Operation
X
1
Maintains previous
switch condition
Latching
X
Reset
X
X
0
0
0
0
1
1
1
1
Transparent Operation
X
TRUTH TABLE - DG529
Differential 4-Channel Multiplexer
EN
WR
RS
On Switch
Logic "0" = V
AL
0.8
V
Logic "1" = V
AH
2.4
V
X = Don’t Care
ORDERING INFORMATION - DG528
Temp Range
0 °C to 70 °C
- 25 °C to 85 °C
- 55 °C to 125 °C
18-pin Cer DIP
Package
18-pin Plastic DIP
20-pin PLCC
Part Number
DG528CJ
DG528DN
DG528BK
DG528AK
DG528AK/883
5962-8768901VA
ORDERING INFORMATION - DG529
Temp Range
0 °C to 70 °C
- 25 °C to 85 °C
- 55 °C to 125 °C
Package
18-pin Plastic DIP
18-pin Cer DIP
Part Number
DG529CJ
DG529BK
DG529AK/883
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltages Referenced to V-
Digital Inputs , V
S
, V
D
Current (Any Terminal Except S or D)
Continuous Current, S or D
Peak Current, S or D (Pulsed at 1 ms, 10 % duty cycle max)
Storage Temperature
(AK, BK Suffix)
(CJ, DN Suffix)
18-pin Plastic DIP
c
Power Dissipation (Package)
b
a
Symbol
V+
GND
Limit
44
25
(V-) - 2 to (V+) + 2
or 30 mA, whichever occurs first
30
20
40
- 65 to 150
- 65 to 125
470
900
800
Unit
V
mA
°C
18-pin CerDIP
20-pin PLCC
e
d
mW
Notes:
a. Signals on S
X
, D
X
or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/°C above 75 °C.
d. Derate 12 mW/°C above 75 °C.
e. Derate 10 mW/°C above 75 °C.
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Document Number: 70068
S11-1029–Rev. D, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG528, DG529
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V, WR = 0,
RS = 2.4 V, V
IN
= 2.4 V, 0.8 µF
f
A Suffix
B, C, D Suffix
- 55 °C to 125 °C - 40 °C to 85 °C
Temp.
b
Full
Room
Full
Room
Room
Full
DG528
DG529
DG528
DG529
Room
Full
Room
Full
Room
Full
Room
Full
Room
Hot
Room
Hot
Room
Hot
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Full
Full
Full
Full
Room
Room
Typ.
c
Min.
d
- 15
270
6
± 005
± 0.015
± 0.008
± 0.03
± 0.015
-1
- 50
- 10
- 200
- 10
- 100
- 10
- 200
- 10
- 100
- 10
- 30
10
30
- 10
- 30
1
1.5
1
µs
- 10
- 30
1
50
10
200
10
100
10
200
10
100
-5
- 50
- 20
- 200
- 20
- 100
- 20
- 200
- 20
- 100
- 10
- 30
10
30
µA
5
50
20
200
20
100
20
200
20
100
Max.
d
15
400
500
Min.
d
- 15
Max.
d
15
450
550
Unit
V
%
Parameter
Analog Switch
Analog Signal Range
e
Drain-Source
On-Resistance
Greatest Change in R
DS(on)
Between Channels
f
Source Off Leakage Current
Symbol
V
ANALOG
R
DS(on)
R
DS(on)
I
S(off)
V
D
= ± 10 V, I
S
= - 200 µA
- 10 V < V
S
< 10 V
V
EN
= 0 V, V
D
= ± 10 V
V
S
= ± 10 V
V
EN
= 0 V, V
D
= ± 10 V
V
S
= ± 10 V
V
S
= V
D
= ± 10 V
V
EN
= 2.4 V
Drain Off Leakage Current
I
D(off)
nA
Drain On Leakage Current
Digital Control
Logic Input Current
I
D(on)
V
A
= 2.4 V
I
AH
V
A
= 15 V
I
AL
t
TRANS
t
OPEN
t
ON(EN,WR)
t
OFF(EN,RS)
Q
OIRR
C
in
C
S(off)
C
D(off)
V
EN
= 0 V, 2.4 V, V
A
= 0 V
RS = 0 V, WR = 0 V
See Figure 5
See Figure 4
See Figure 6 and 7
See Figure 6 and 8
V
S
= 0 V, R
y
= 0
C
L
= 10
F
V
EN
= 0 V, R
L
= 1 kC
L
= 15 pF
V
S
= 7 V
RMS
, f = 500 kHz
f = 1 MHz
V
EN
= 0 V, V
D
= 0 V, f = 140 kHz
DG528
V
EN
= 0 V, V
D
= 0 V
f = 140 kHz
DG529
- 0.002
0.006
- 0.002
Input Voltage High
Logic Input Current
Input Voltage Low
Dynamic Characteristics
Transition Time
Break-Before-Make Interval
EN and WR Turn-On Time
EN and WR Turn-Off Time
Charge Injection
Off Isolation
Logic Imput Capacitance
Source Off Capacitance
Drain Off Capacitance
0.6
0.2
1
0.4
4
68
2.5
5
25
12
300
180
30
500
pC
dB
pF
Minimum Input Timing Requirements
t
W
Write Pulse Width
t
S
A
X
, EN Data Set Up time
t
H
A
X
, EN Data Hold Time
Reset Pulse Width
t
RS
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I-
V
S
= 5 V, See Figure 3
V
EN
= V
A
= 0 V
300
180
30
500
2.5
2.5
- 1.5
ns
- 1.5
mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. V
IN
= input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 70068
S11-1029–Rev. D, 23-May-11
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG528, DG529
Vishay Siliconix
TYPICAL CHARACTERISTICS
(T
A
= 25 °C, unless noted)
500
R
DS(on)
– Drain-Source On-Resistance (Ω)
T
A
= 25 °C
400
± 7.5 V
I S, I D (pA)
- 20
I
D(off)
I
S(off)
I
D(on)
0
300
± 10 V
200
± 15 V
- 40
± 15 V Supplies
T
A
= 25
± 20 V
100
- 20
- 15
- 10
-5
0
5
10
15
20
V
D
– Drain Voltage (V)
- 60
- 15
- 10
-5
0
5
10
15
V
ANALOG
– Analog Voltage (V)
R
DS(on)
vs. V
D
and Power Supply
2.5
T
A
= 25 °C
2.0
3
I+, I- (mA)
V T (V)
1.5
4
Leakage Currents vs. Analog Voltage
I+
2
1.0
0.5
1
I-
0
0
0
±5
± 10
± 15
± 20
1k
10 k
100 k
1M
V+, V- Positive and Negative Supplies (V)
Toggle Frequency (Hz)
Input Switching Threshold vs.
V+ and V- Supply Voltages
Supply Currents vs. Toggle Frequency
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Document Number: 70068
S11-1029–Rev. D, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG528, DG529
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
GND
V
REF
V+
EN
V+
V-
A
X
V+
V-
WR
V+
V-
RS
V-
V+
CLK
RESET
D
O
Q
O
V-
V+
D
n
Q
n
V-
V+
V-
Latches
Level
Shift
Decode
V-
S
1
S
n
V+
D
Figure 1.
DETAILED DESCRIPTION
The internal structure of the DG528/DG529 includes a 5-V
logic interface with input protection circuitry followed by a
latch, level shifter, decoder and finally the switch constructed
with parallel n- and p-channel MOSFETs (see Figure 1).
The logic interface circuit compares the TTL input signal
against a TTL threshold reference voltage. The output of the
comparator feeds the data input of a D type latch. The level
sensitive D latch continuously places the D
X
input signal on
the Q
X
output when the WR input is low, resulting in transpar-
ent latch operation. As soon as WR returns high, the latches
hold the data last present on the D
X
input, subject to the mini-
mum input timing requirements.
3V
WR
0
t
W
t
S
3V
A
0
, A
1
, (A
2
)
EN
0
t
H
50 %
Following the latches the Q
X
signals are level shifted and
decoded to provide proper drive levels for the CMOS
switches. This level shifting insures full on/off switch operation
for any analog signal present between the V+ and V- supply
rails.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard-wired to the logic supply or to V+ if
one of the channels will always be used (except during a reset)
or it can be tied to address decoding circuitry for memory
mapped operation. The RS pin is used as a master reset. All
latches are cleared regardless of the state of any other latch
or control line. The WR pin is used to transfer the state of the
address control lines to their latches, except during a reset or
when EN is low (see Truth Tables).
3V
RS
0
t
RS
t
OFF (RS)
Switch
Output
V
O
80 %
0
50 %
80 %
80 %
Figure 2.
Figure 3.
Document Number: 70068
S11-1029–Rev. D, 23-May-11
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5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
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