Preliminary
FM25C160C
16Kb Serial 5V F-RAM Memory
Features
16K bit Ferroelectric Nonvolatile RAM
Organized as 2,048 x 8 bits
High Endurance 1 Trillion (10
12
) Read/Writes
36 year Data Retention at +75C
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
Up to 20 MHz maximum Bus Frequency
Direct hardware replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Sophisticated Write Protection Scheme
Hardware Protection
Software Protection
Low Power Consumption
250
A
Active Current (1 MHz)
4
A
(typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
8-pin “Green”/RoHS SOIC (-G)
Description
The FM25C160C is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 36 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
The FM25C160C performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM25C160C is capable of
supporting up to 10
12
read/write cycles, or a million
times more write cycles than EEPROM.
These capabilities make the FM25C160C ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25C160C provides substantial benefits to
users of serial EEPROM, in a hardware drop-in
replacement. The FM25C160C uses the high-speed
SPI bus, which enhances the high-speed write
capability of F-RAM technology. The specifications
are guaranteed over an industrial temperature range
of -40°C to +85°C.
Pin Configuration
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VDD
HOLD
SCK
SI
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
5V
Ground
Ordering Information
FM25C160C-G
FM25C160C-GTR
“Green” 8-pin SOIC
“Green” 8-pin SOIC,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.1
July 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-F-RAM, (719) 481-7000
www.ramtron.com
Page 1 of 13
FM25C160C - 16Kb 5V SPI F-RAM
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
256 x 64
FRAM Array
Instruction Register
Address Register
Counter
SI
11
8
Data I/O Register
3
Nonvolatile Status
Register
SO
Figure 1. Block Diagram
Pin Description
Pin Name
/CS
I/O
Input
Pin Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the status register. This
is critical since other write protection features are controlled through the status
register. A complete explanation of write protection is provided on page 6. *Note that
the function of /WP is different from the FM25160.
Serial Input: All data is input to the device on this pin. The pin is sampled on the rising
edge of SCK and is ignored at other times. It should always be driven to a valid logic
level to meet I
DD
specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output. SO is the data output pin. It is driven actively during a read and remains
tri-state at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Supply Voltage. 5V
Ground
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Rev. 1.1
July 2011
Page 2 of 13
FM25C160C - 16Kb 5V SPI F-RAM
Overview
The FM25C160C is a serial F-RAM memory. The
memory array is logically organized as 2,048 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to serial EEPROMs. The
major difference between the FM25C160C and a
serial EEPROM with the same pin-out relates to its
superior write performance. This makes the
FM25C160C a drop-in replacement for most 16Kb
SPI EEPROMs that support modes 0 & 3.
Serial Peripheral Interface – SPI Bus
The FM25C160C employs a Serial Peripheral
Interface (SPI) bus. It is specified to operate at speeds
up to 20 MHz. This high-speed serial bus provides
high performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25C160C operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25C160C devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25C160C device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins (SI, SO) together and tie
off (high) the Hold pin. Figure 3 shows a
configuration that uses only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25C160C will begin
monitoring the clock and data lines. The relationship
between the falling edge of /CS, the clock and data is
dictated by the SPI mode. The device will make a
determination of the SPI mode on the falling edge of
each chip select. While there are four such modes, the
FM25C160C supports modes 0 and 3. Figure 4 shows
the required signal relationships for modes 0 and 3.
For both modes, data is clocked into the FM25C160C
on the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After /CS
is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Important: The /CS pin must go inactive after an
operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
Memory Architecture
When accessing the FM25C160C, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code and a
two-byte address. The upper 5 bits of the address
range are „don‟t care‟ values. The complete address
of 11-bits specifies each byte address uniquely.
Most functions of the FM25C160C either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation essentially is zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation will be
complete. This is explained in more detail in the
interface section below.
Users expect several obvious system benefits from
the FM25C160C due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note: The FM25C160C contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within data sheet tolerances to
prevent incorrect operation. It is recommended
that the part is not powered down with chip
enable active.
Rev. 1.1
July 2011
Page 3 of 13
FM25C160C - 16Kb 5V SPI F-RAM
SCK
MOSI
MISO
SO
SI SCK
SO
SI SCK
SPI
Microcontroller
SS1
SS2
HOLD1
HOLD2
MOSI: Master Out, Slave In
MISO: Master In, Slave Out
SS: Slave Select
FM25C160C
CS
HOLD
FM25C160C
CS
HOLD
Figure 2. System Configuration with SPI port
Microcontroller
SO
SI SCK
FM25C160C
CS
HOLD
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 1.1
July 2011
Page 4 of 13
FM25C160C - 16Kb 5V SPI F-RAM
Data Transfer
All data transfers to and from the FM25C160C occur
in 8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. Serial inputs are clocked in on the rising
edge of SCK. Outputs are driven on the falling edge
of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25C160C. They
are listed in the table below. These op-codes control
the functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operations. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register. Last are
commands for memory transactions followed by
address and one or more bytes of data.
Table 1. Op-code Commands
Name
Description
WREN
WRDI
RDSR
WRSR
READ
WRITE
Set Write Enable Latch
Write Disable
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
WREN - Set Write Enable Latch
The FM25C160C will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the status register
and writing the memory.
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted. A write to
the status register has no effect on the WEL bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further writes
without another WREN command. Figure 5 below
illustrates the WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
status register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
Op-code value
0000
_
0110b
0000
_
0100b
0000
_
0101b
0000
_
0001b
0000
_
0011b
0000
_
0010b
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Rev. 1.1
July 2011
Page 5 of 13
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