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APU429

Description
4-Bit Micro-controller With LCD Driver
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size197KB,18 Pages
ManufacturerAplus
Websitehttp://www.aplusinc.com.tw/
Download Datasheet Parametric View All

APU429 Overview

4-Bit Micro-controller With LCD Driver

APU429 Parametric

Parameter NameAttribute value
MakerAplus
package instruction,
Reach Compliance Codeunknow
4-Bit Micro-controller With LCD Driver
Features
Low power and low voltage operation
Powerful instruction set (150 instructions)
Memory capacity
Instruction ROM capacity 4096 x 16 bits
Index ROM capacity 256 x 8 bits
Internal RAM capacity 384 or 256 x 4 bits
Input/Output ports of up to 20 pins
8-level subroutine nesting
Built-in LCD driver, 8 x 42 = 336 segments
Built-in EL driver, frequency or melody generator
Built-in Resistance-to-Frequency Converter
Built-in 2-channel 6/8-bit PWM output
Built-in key strobe function
(Shared with segment pin)
Built-in voltage doubler, halver, tripler
quadrupler charge pump circuit
Two 6-bit programmable timers with
programmable clock source
Watchdog timer
4 external & 3 internal interrupt resources
External: INT, RFC, IOA/IOC/S port,
keystrobe
Internal: TM1, TM2, Predivider
Dual clock operation
HALT and STOP function
General Description
The
APU429
is an embedded high performance
4-bit micro-computer with an on-chip LCD driver. It
contains all the necessary functions in a single chip:
4-bit parallel processing ALU, ROM, RAM, I/O ports,
timer, clock generator, dual clock, RFC, EL-light,
LCD driver, look-up table, watchdog timer and
keyboard scanning. The instruction set includes not
only 4-bit operation and manipulation instructions
but also various conditional branch instructions and
LCD driver data transfer instructions which are
powerful and easy to use.
The HALT function stops any internal operations
other than the oscillator, divider and LCD driver in
order to minimize the power dissipation.
The STOP function stops all the clocks in the chip.
Block Diagram
S E G 35 38
S E G 31 34
S E G 39 42
S E G 27 30
COM 1 8
S E G 1 S E G 26
VDD1 4
IO A P o rt
/R F C
IO B P o rt
/E L , B Z
IO C P o rt
/K E Y IN
IO D P o rt
/P W M
L C D D ri r
ve
S egm entP LA
4 -B i D a ta B u s
t
F re q u e n cy
G e n e ra to r
T abl R O M
e
256 x 8
In d e x S R A M
256 x 4
SRAM
128 x 4
A LU
CUP 1
CUP 2
CUP 3
P re -D i d e r
vi
2 x 6 Bi
ts
P re se t T i e r
m
8 -L e ve l S ta ck
s
In stru cti n
o
D e co d e r
W a tch d o g
T i er
m
O scil to r
la
X TO U T
C FO U T
C o n tro l
Ci i
rcu t
1 2 -B i P ro g ra m
t
C o u n te r
M a sk R O M
4096 x 16
RESET
Preliminary
C FI
N
X TI
N
I T
N
S1 S4
1
Ver. 0.0
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