SFX-424G
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Applications
•
SONET / SDH / ATM
•
DWDM / FDM
•
FEC (Forward Error Correction)
Features
•
3.3V High Precision PLL
•
Jitter Generation OC-192 Compliant
•
Surface Mount
•
Accepts up to 4 Inputs from an External MUX
•
Inputs Compatible with CMOS/LVDS/LVPECL
•
Frequency Translation up to 800 MHz
•
Alarm detection for Loss of Lock/ Loss of Reference condition
•
ROHS Compliant
Bulletin
Page
Revision
Date
Issued By
SG124
1 of 8
00
09 DEC 08
ENG
General Description
The SFX-424G is a high precision frequency translator that
translates up to four inputs from 8 kHz to 100MHz , to output
frequencies between 8 MHz and 800 MHz. The SFX-424G
supports all major FEC rates such as 15/14, 255/237 etc.
SFX-424G is well suited for use in line cards, service
termination cards and similar functions to provide reliable
reference, phase locked, synchronization for TDM, PDH,
SONET and SDH network equipment. The SFX-424G provides
a jitter filtered, wander following output signal synchronized to
a superior Stratum or peer input reference signal.
The SFX-424G includes a lock detect alarm output.
The PLL control voltage is brought out through a 470 kΩ
resistor and can be used to determine when the pull
range limits are reached. The LVPECL outputs may be
put into the tri-state high impedance condition for
external testing purposes by asserting a high signal to
the Enable/Disable pin.
Parts are assembled using high temperature solder to
withstand surface mount reflow process. This product is
compliant with all required ROHS specifications.
Absolute Maximum Rating
Table 1
Symbol
Vcc
VI
Ts
Parameter
Power Supply Voltage (OptionD)
Input Voltage
Storage Temperature (OptionF)
Storage Temperature (OptionA)
Minimum
-0.3
-0.2
-55
-40
Nominal
-
-
-
-
Maximum
4.0
Vcc +0.3V
125
85
Units
Volts
Volts
°C
°C
Notes
Specifications
Table 2
Symbol
f
IN
f
OUT
Vcc
I
CC
V
IH
V
IL
LVPECL INPUT
V
IH
V
IL
LVCMOS OUTPUT (Option A)
LVPECL OUTPUT (Option F)
V
OH
V
OL
V
OH
V
OL
T
R
/T
F
SYM
J
GEN
J
TRAN
APR
T
OP
(Temp. Range
C
= 0°C to 70°C)
(Temp. Range
C
= 0°C to 70°C)
(Temp. Range
F
= -40°C to 85°C)
(Temp. Range
F
= -40°C to 85°C)
Rise/Fall Time @20% to 80%
Output Symmetry
Jitter Generation RMS
(12 kHz - 20 MHz)
Jitter Transfer
Input Frequency Tracking
Operating Temperature
F
=
C
=
2.275
-
2.275
-
-
45
-
-
±40
-40
0
-
-
-
-
-
85
70
-
-
-
-
0.6
1.68
1.68
1.5
55
1
0.1
V
V
V
V
ns
%
ps
dB
ppm
°C
°C
1.0
1.49
0.86
-
-
TYP. LVCMOS
2.72
2.125
Volts
Volts
Parameter
Input Frequencies
Output Frequencies (LVPECL)
Output Frequencies (LVCMOS)
Supply Voltage (3.3 V
DC
)
Supply Current
Minimum
8k
19.44 M
8M
3.13
-
2
-0.3
Nominal
-
-
-
3.3
60
-
-
Maximum
100 M
800 M
130 M
3.46
-
VCC
0.8
Units
Hz
Hz
Hz
Volts
mA
Volts
Volts
Notes
LVCMOS INPUT
NOTES: 1.0: GR-253-CORE, Sec. 5.6.2.1.2
Data Sheet #:
SG124
Page 2
of
8
Rev:
00
Date:
12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Functional Block Diagram
Figure 1
LD
(Pin 10)
470 kΩ
V
MON
(Pin 5)
F
IN
(Pin 13)
Frequency
0.01
µF
Loop
Filter
OSC
F
OUT
(Pin 8)
Divider
CF
Out
(Pin 9)
Frequency
10 kΩ
Divider
SEL0
(Pin 1)
Microprocessor
10 kΩ
SEL1
(Pin 2)
OD
(Pin 6)
Pin Description
Table 3
PIN # SYMBOL
1
2
3
4
5
VMON
O
Analog
I/O
I
I
GND
Level
LVTTL
LVTTL
Supply
Function
Input Frequency Select .* 10kΩ Pull down resistor
Ω
Input Frequency Select .* 10kΩ Pull down resistor
Ground
Missing
VCXO Control VoltageUnder locked conditions VMON should
be > 0.3V and <3.0V. The Input Frequency may be out of
range if the voltage is outside of this voltage range.
Output Disable
Disable = Logic 1
Enable = Logic 0 or No Connect
Ground
Frequency Output
Complementary Frequency Output
Note: For the LVCMOS Option, this
connection is tied to GND
Lock Detect
Locked = Logic 1
Loss of Signal = Logic 0
Ground
Ground
Input FrequencyNote: Input is AC coupled
for handling either LVCMOS or LVPECL input signals
Power Supply Voltage (3.3V ±5%)
SEL0
SEL1
GND
6
OD
I
LVCMOS
7
8
9
GND
FOUT
CFOUT
GND
O
O
Supply
LVPECL or LVCMOS
LVPECL or GND
10
LD
O
LVCMOS
11
12
13
14
GND
GND
FIN
VCC
GND
GND
I
VCC
Supply
Supply
LVPECL or LVCMOS
Supply
Data Sheet #:
SG124
Page 3
of
8
Rev:
00
Date:
12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Output Load and Power Supply Filtering Recommendations
Figure 2
*
It is highly recommended
that either a linear regulator
or bypass capacitors be
used. Typical values would
be 10 uF, 0.1 uF, 100 pF.
*
*
*
Only Required for Option F
V
CC
-2 V
DC
LD
(Pin 10)
470 kΩ
V
MON
(Pin 5)
50Ω
50Ω
REF 1
REF 2
REF 3
REF 4
IN
(Pin 13)
0.01
µF
F
Frequency
Divider
Loop
Filter
OSC
F
OUT
(Pin 8)
CF
OUT
(Pin 9)
Frequency
SEL0
(Pin 1)
10 kΩ
Divider
Microprocessor
SEL1
(Pin 2)
10 kΩ
OD
(Pin 6)
Package Dimensions
Figure 3
Recommended Footprint Dimensions
Figure 4
mm
[ inches ]
19.81
.780
20.32
.800
13.72
.540
PIN 1
2.54
.100
12.19
.480
5.84
.230
12.446
[0.490]
C
L
mm
(in)
1.905
[0.075]
3.048
[0.120]
R 0.51
.020
4.29
.169
7.620
[0.300]
C
L
15.240
[0.600]
2.540
[0.100]
Data Sheet #:
SG124
6.223
[0.245]
Page 4
of
8
Rev:
00
Date:
12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
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