Preliminary Information
512K
X24513
1MHz 2-Wire Serial EEPROM with Block Lock
™
DESCRIPTION
64K x 8 Bit
FEATURES
• Save critical data with programmable block lock
protection
—Block lock (first page, first 2 pages, first 4
pages, first 8 pages, 1/4, 1/2, or all of EEPROM
array)
—Software write protection
—Programmable hardware write protect
• In circuit programmable ROM mode
• 1MHz 2-wire serial interface
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
• Longer battery life with lower power
—Active read current less than 1µA
—Active write current less than 3µA
—Standby current less than 1µA
• 2.5V to 5.5V power supply versions
• 128-byte page write mode
—Minimizes total write time per word
• Internally organized 64K x 8
• Bidirectional data transfer protocol
• Self-timed write cycle
—Typical write cycle time of 5ms
• High reliability
—Endurance: 100,000 cycles
—Data retention: 100 years
• 8-lead XBGA, 20-lead SOIC (JEDEC),
20-lead TSSOP
The X24513 is a CMOS Serial EEPROM, internally
organized 64K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
Two device select inputs (S
0
–S
1
) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address location,
FFFFh, provides three write protection features: Software
Write Protect, Block Lock Protect, and Programmable
Hardware Write Protect. The Software Write Protect
feature prevents any nonvolatile writes to the device
until the WEL bit in the Write Protect Register is set.
The Block Lock Protection feature gives the user eight
array block protect options, set by programming three
bits in the Write Protect Register. The Programmable
Hardware Write Protect feature allows the user to
install the device with WP tied to V
CC
, write to and
Block Lock the desired portions of the memory array in
circuit, and then enable the In Circuit Programmable
ROM Mode by programming the WPEN bit HIGH in the
Write Protect Register. After this, the Block Locked
portions of the array, including the Write Protect Register
itself, are protected from being erased if WP is high.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Serial EEPROM Data
and Address (SDA)
SCL
Command
Decode
and
Control
Logic
Block Lock and
Write Protect
Control Logic
S
1
S
0
Device
Select
Logic
Write
Protect
Register
Page
Decode
Logic
Data Register
Y Decode Logic
Serial EEPROM
Array
64K X 8
WP
Write Voltage
Control
REV 1.1 9/8/00
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Characteristics subject to change without notice.
1 of 18
X24513 – Preliminary Information
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S
0
, S
1
)
The device select inputs (S
0
, S
1
) are used to set bits in
the slave address. This allows up to 4 devices to share
a common bus. These inputs can be static or actively
driven. If used statically they must be tied to V
SS
or
V
CC
as appropriate. If actively driven, they must be
driven with CMOS levels (driven to V
CC
or V
SS
) and
they must be constant between each start and stop
issued on the SDA bus. These pins have an active pull
down internally and will be sensed as low if the pin is
left unconnected.
Write Protect (WP)
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Protect
feature. When held LOW, Hardware Write Protection is
disabled. When this input is held HIGH, and the WPEN
bit in the Write Protect Register is set HIGH, the Write
Protect Register is protected, preventing changes to
the Block Lock Protection and WPEN bits.
PIN NAMES
Symbol
S
0
, S
1
SDA
SCL
WP
V
SS
V
CC
NC
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
No Connect
PIN CONFIGURATION
8-Lead XBGA: Top View
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
S
1
S
0
NC
V
SS
20-Pin JEDEC SOIC/20-Pin TSSOP
S
0
S
1
NC
NC
NC
NC
NC
NC
NC
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
WP
NC
NC
NC
NC
NC
NC
SCL
SDA
REV 1.1 9/8/00
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Characteristics subject to change without notice.
2 of 18
X24513 – Preliminary Information
DEVICE OPERATION
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
Start Bit
Stop Bit
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
REV 1.1 9/8/00
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
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Characteristics subject to change without notice.
3 of 18
X24513 – Preliminary Information
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
fromReceiver
Start
Acknowledge
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next bit is a “0”. The
next 2 bits are the device select bits S
0
and S
1
. This
allows up to 4 devices to share a single bus. These bits
are compared to the S
0
and S
1
device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a write operation is selected. Refer to Figure 4. After
loading the Slave Address Byte from the SDA bus, the
device compares the device type bits with the value
“1010” and the device select bits with the status of the
device select input pins. If the compare is not success-
ful, no acknowledge is output during the ninth clock
cycle and the device returns to the standby mode.
On power up the internal address is undefined, so the
first read or write operation must supply an address.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
The internal organization of the E
2
array is 512 pages
by 128 bytes per page. The page address is contained
in the Word Address Byte 1 and in bit 7 of the Word
Address Byte 0. The byte address is contained in bit 6
through 0 of the Word Address Byte 0. See Figure 4.
The read and write of the last data byte on memory (at
FFFFh) can only be performed indirectly.
Figure 4. Device Addressing
Device Type
Identifier
Device
Select
1
0
1
0
0
S
1
S
0
R/W
Slave Address Byte
High Order Word Address
A15
A14 A13 A12
A11 A10
A9
A8
X24513 Word Address Byte 1
Low Order Word Address
A7
A6
A5
A4
A3
A2
A1
A0
Word Address Byte 0
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
REV 1.1 9/8/00
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Characteristics subject to change without notice.
4 of 18
X24513 – Preliminary Information
WRITE OPERATIONS
Byte Write
For a write operation, the device follows “3 byte” proto-
col, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 5.
Page Write
The device is capable of a 128-byte page write opera-
tion. It is initiated in the same manner as the byte write
operation; but instead of terminating the write operation
Figure 5. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
T
A
R
T
Word Address
Byte 1
Word Address
Byte 0
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
after the first data word is transferred, the master can
transmit up to sixty-three more words. The device will
respond with an acknowledge after the receipt of each
word, and then the byte address is internally incre-
mented by one. The page address remains constant.
When the counter reaches the end of the page, it “rolls
over” and goes back to the first byte of the current
page. This means that the master can write 128-bytes
to the page beginning at any byte. If the master begins
writing at byte 64, and loads 128-bytes, then the first
64-bytes are written to bytes 64 through 127, and the
last 16 words are written to bytes 0 through 63. After-
wards, the address counter would point to byte 64. If the
master writes more than 128-bytes, then the previously
loaded data is overwritten by the new data, one byte at
a time.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 6 for the address, acknowl-
edge, and data transfer sequence.
Slave
Address
0
Data
S1 0 1 0
Figure 6. Page Write Sequence
(0
≤
n
≤
64)
Signals from
the Master
S
T
A
R
T
Slave
Address
0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Word Address
Byte 1
Word Address
Byte 0
Data
(0)
Data
(n)
S
T
O
P
P
SDA Bus
Signals from
the Slave
S 1 0 1 0
REV 1.1 9/8/00
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Characteristics subject to change without notice.
5 of 18
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