Circuits with a direct battery or power source connection.
Critical and safety relevant circuits without (integrated) current
limitation.
• Any application that is subject to high levels of board flexure or
temperature cycling
Ordering Information
C
Ceramic
2220
C
106
Capacitance
Code (pF)
2 Sig. Digits
+ Number of
Zeros
M
Capacitance
Tolerance
1
K = ±10%
M = ±20%
5
Voltage
8 = 10V
4 = 16V
3 = 25V
5 = 50V
1 = 100V
A = 250V
R
Dielectric
R = X7R
2
Failure Rate/Design
1 = KPS Single Chip Stack
2 = KPS Double Chip Stack
C
TU
Case Size Specification/
(L" x W")
Series
1210
1812
2220
C = Standard
End
Packaging/Grade
2
Metallization
(C-Spec)
3
C = 100%
Matte Sn
TU = 7" Reel
Unmarked
7289 = 13" Reel
Unmarked
Double chip stacks ("2" in the 13th character position of the ordering code) are only available in M (±20%) capacitance tolerance. Single chip stacks ("1" in
the 13th character position of the ordering code) are available in K (±10%) or M (±20%) tolerances.
2
Additional termination options may be available. Contact KEMET for details.
3
Additional reeling or packaging options may be available. Contact KEMET for details.
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FPGA/CPLD
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