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Intel
®
925X/925XE Express
Chipset
Datasheet
For the Intel
®
82925X/82925XE Memory Controller Hub (MCH)
November 2004
Document Number:
301464-003
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
82925X/82925XE MCH may contain design defects or errors known as errata, which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Ω
Look for systems with the Intel® Pentium® 4 Processor with HT Technology logo and also including an Intel® 925, 915, or 910 Express Chipset
(see the product spec sheet or ask your salesperson). Performance and functionality will vary depending on (i) the specific hardware and software
you use and (ii) the feature enabling/system configuration by your system vendor. See
www.intel.com/products/ht/hyperthreading_more.htm
for
information on HT Technology or consult your system vendor for more information.
Φ
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS.
Performance will vary depending on your hardware and software configurations. See
www.intel.com/info/em64t
for more information including
details on which processors support EM64T or consult with your system vendor for more information.
Intel and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright
©
2004, Intel Corporation
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Intel
®
82925X/82925XE MCH Datasheet
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Contents
1
Introduction ....................................................................................................................... 13
1.1
1.2
1.3
Terminology.......................................................................................................... 15
Reference Documents.......................................................................................... 16
MCH Overview ..................................................................................................... 16
1.3.1
Host Interface........................................................................................ 16
1.3.2
System Memory Interface..................................................................... 17
1.3.3
Direct Media Interface (DMI)................................................................. 18
1.3.4
PCI Express* Graphics Interface .......................................................... 18
1.3.5
System Interrupts.................................................................................. 19
1.3.6
MCH Clocking ....................................................................................... 20
1.3.7
Power Management.............................................................................. 20
Host Interface Signals .......................................................................................... 23
DDR2 DRAM Channel A Interface ....................................................................... 26
DDR2 DRAM Channel B Interface ....................................................................... 27
DDR2 DRAM Reference and Compensation....................................................... 28
PCI Express* x16 Graphics Port Signals ............................................................. 28
Clocks, Reset, and Miscellaneous ....................................................................... 29
Direct Media Interface (DMI) ................................................................................ 29
Power and Ground ............................................................................................... 30
Reset States and Pull-up/Pull-downs................................................................... 30
2
Signal Description ............................................................................................................. 21
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Register Description.......................................................................................................... 35
3.1
3.2
3.3
Register Terminology ........................................................................................... 35
Platform Configuration.......................................................................................... 37
General Routing Configuration Accesses ............................................................ 38
3.3.1
Standard PCI Bus Configuration Mechanism ....................................... 38
3.3.2
Logical PCI Bus 0 Configuration Mechanism ....................................... 39
3.3.3
Primary PCI and Downstream Configuration Mechanism .................... 39
3.3.4
PCI Express* Enhanced Configuration Mechanism ............................. 40
3.3.5
Intel
®
82925X/925XE MCH Configuration Cycle Flowchart ................. 42
I/O Mapped Registers .......................................................................................... 43
3.4.1
CONFIG_ADDRESS—Configuration Address Register ...................... 43
3.4.2
CONFIG_DATA—Configuration Data Register .................................... 44
Device 0 Function 0 PCI Configuration Register Details ..................................... 48
4.1.1
VID—Vendor Identification (D0:F0) ...................................................... 48
4.1.2
DID—Device Identification (D0:F0) ...................................................... 48
4.1.3
PCICMD—PCI Command (D0:F0) ....................................................... 49
4.1.4
PCISTS—PCI Status (D0:F0)............................................................... 50
4.1.5
RID—Revision Identification (D0:F0).................................................... 51
4.1.6
CC—Class Code (D0:F0) ..................................................................... 51
3.4
4
Host Bridge/DRAM Controller Registers (D0:F0) ............................................................. 45
4.1
Intel
®
82925X/82925XE MCH Datasheet
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4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.1.16
4.1.17
4.1.18
4.1.19
4.1.20
4.1.21
4.1.22
4.1.23
4.1.24
4.1.25
4.1.26
4.1.27
4.1.28
4.1.29
4.1.30
4.1.31
4.1.32
4.1.33
4.1.34
4.1.35
4.1.36
5
5.1
MLT—Master Latency Timer (D0:F0)................................................... 52
HDR—Header Type (D0:F0) ................................................................ 52
SVID—Subsystem Vendor Identification (D0:F0)................................. 52
SID—Subsystem Identification (D0:F0)................................................ 53
CAPPTR—Capabilities Pointer (D0:F0) ............................................... 53
EPBAR—Egress Port Base Address (D0:F0) ...................................... 54
MCHBAR—MCH Memory Mapped Register Range Base Address
(D0:F0).................................................................................................. 55
PCIEXBAR—PCI Express* Register Range Base Address (D0:F0) ... 56
DMIBAR—Root Complex Register Range Base Address (D0:F0) ...... 57
DEVEN—Device Enable (D0:F0) ......................................................... 58
DEAP—DRAM Error Address Pointer (D0:F0) (Intel
®
82925X Only)... 59
DERRSYN—DRAM Error Syndrome (D0:F0) (Intel
®
82925X Only) .... 60
DERRDST—DRAM Error Destination (D0:F0) (Intel
®
82925X Only)... 61
PAM0—Programmable Attribute Map 0 (D0:F0) .................................. 62
PAM1—Programmable Attribute Map 1 (D0:F0) .................................. 63
PAM2—Programmable Attribute Map 2 (D0:F0) .................................. 64
PAM3—Programmable Attribute Map 3 (D0:F0) .................................. 65
PAM4—Programmable Attribute Map 4 (D0:F0) .................................. 66
PAM5—Programmable Attribute Map 5 (D0:F0) .................................. 67
PAM6—Programmable Attribute Map 6 (D0:F0) .................................. 68
LAC—Legacy Access Control (D0:F0) ................................................. 69
TOLUD—Top of Low Usable DRAM (D0:F0) ....................................... 70
SMRAM—System Management RAM Control (D0:F0)........................ 71
ESMRAMC—Extended System Management RAM Control (D0:F0) .. 72
ERRSTS—Error Status (D0:F0) ........................................................... 72
ERRCMD—Error Command (D0:F0) ................................................... 74
SMICMD—SMI Command (D0:F0) ...................................................... 75
SCICMD—SCI Command (D0:F0) ....................................................... 76
SKPD—Scratchpad Data (D0:F0) ........................................................ 76
CAPID0—Capability Identifier (D0:F0) ................................................. 77
MCHBAR Registers .......................................................................................................... 79
MCHBAR Register Details ................................................................................... 80
5.1.1
C0DRB0—Channel A DRAM Rank Boundary Address 0 .................... 80
5.1.2
C0DRB1—Channel A DRAM Rank Boundary Address 1 .................... 82
5.1.3
C0DRB2—Channel A DRAM Rank Boundary Address 2 .................... 82
5.1.4
C0DRB3—Channel A DRAM Rank Boundary Address 3 .................... 82
5.1.5
C0DRA0—Channel A DRAM Rank 0,1 Attribute ................................. 83
5.1.6
C0DRA2—Channel A DRAM Rank 2,3 Attribute ................................. 83
5.1.7
C0DCLKDIS—Channel A DRAM Clock Disable .................................. 84
5.1.8
C0BNKARC—Channel A DRAM Bank Architecture ............................ 85
5.1.9
C0DRT1—Channel A DRAM Timing Register ..................................... 86
5.1.10 C0DRC0—Channel A DRAM Controller Mode 0 ................................. 88
5.1.11 C1DRB0—Channel B DRAM Rank Boundary Address 0 .................... 90
5.1.12 C1DRB1—Channel B DRAM Rank Boundary Address 1 .................... 90
5.1.13 C1DRB2—Channel B DRAM Rank Boundary Address 2 .................... 90
5.1.14 C1DRB3—Channel B DRAM Rank Boundary Address 3 .................... 90
5.1.15 C1DRA0—Channel B DRAM Rank 0,1 Attribute ................................. 90
5.1.16 C1DRA2—Channel B DRAM Rank 2,3 Attribute ................................. 91
5.1.17 C1DCLKDIS—Channel B DRAM Clock Disable .................................. 91
5.1.18 C1BNKARC—Channel B Bank Architecture ........................................ 91
5.1.19 C1DRT1—Channel B DRAM Timing Register 1 .................................. 91
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Intel
®
82925X/82925XE MCH Datasheet
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5.1.20
5.1.21
5.1.22
6
6.1
C1DRC0—Channel B DRAM Controller Mode 0 ................................. 91
PMCFG—Power Management Configuration ...................................... 92
PMSTS—Power Management Status .................................................. 92
EPBAR Registers—Egress Port Register Summary ........................................................ 93
EP RCRB Configuration Register Details ............................................................ 93
6.1.1
EPESD—EP Element Self Description................................................. 94
6.1.2
EPLE1D—EP Link Entry 1 Description ................................................ 95
6.1.3
EPLE1A—EP Link Entry 1 Address...................................................... 95
6.1.4
EPLE2D—EP Link Entry 2 Description ................................................ 96
6.1.5
EPLE2A—EP Link Entry 2 Address...................................................... 97
Direct Media Interface (DMI) RCRB Register Details ........................................ 100
7.1.1
DMIVCECH—DMI Virtual Channel Enhanced Capability Header ..... 100
7.1.2
DMIPVCCAP1—DMI Port VC Capability Register 1 .......................... 100
7.1.3
DMIPVCCAP2—DMI Port VC Capability Register 2 .......................... 101
7.1.4
DMIPVCCTL—DMI Port VC Control .................................................. 101
7.1.5
DMIVC0RCAP—DMI VC0 Resource Capability ................................ 102
7.1.6
DMIVC0RCTL0—DMI VC0 Resource Control ................................... 103
7.1.7
DMIVC0RSTS—DMI VC0 Resource Status....................................... 104
7.1.8
DMIVC1RCAP—DMI VC1 Resource Capability ................................ 104
7.1.9
DMIVC1RCTL1—DMI VC1 Resource Control ................................... 105
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status....................................... 106
7.1.11 DMILCAP—DMI Link Capabilities ...................................................... 106
7.1.12 DMILCTL—DMI Link Control .............................................................. 107
7.1.13 DMILSTS—DMI Link Status ............................................................... 107
Device 1 Configuration Register Details ............................................................ 112
8.1.1
VID1—Vendor Identification (D1:F0) .................................................. 112
8.1.2
DID1—Device Identification (D1:F0) .................................................. 112
8.1.3
PCICMD1—PCI Command (D1:F0) ................................................... 113
8.1.4
PCISTS1—PCI Status (D1:F0)........................................................... 114
8.1.5
RID1—Revision Identification (D1:F0)................................................ 116
8.1.6
CC1—Class Code (D1:F0) ................................................................. 116
8.1.7
CL1—Cache Line Size (D1:F0) .......................................................... 117
8.1.8
HDR1—Header Type (D1:F0) ............................................................ 117
8.1.9
PBUSN1—Primary Bus Number (D1:F0) ........................................... 117
8.1.10 SBUSN1—Secondary Bus Number (D1:F0) ...................................... 118
8.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ................................. 118
8.1.12 IOBASE1—I/O Base Address (D1:F0) ............................................... 119
8.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................ 119
8.1.14 SSTS1—Secondary Status (D1:F0) ................................................... 120
8.1.15 MBASE1—Memory Base Address (D1:F0)........................................ 121
8.1.16 MLIMIT1—Memory Limit Address (D1:F0)......................................... 122
8.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ................ 123
8.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) ................. 124
8.1.19 CAPPTR1—Capabilities Pointer (D1:F0) ........................................... 124
8.1.20 INTRLINE1—Interrupt Line (D1:F0) ................................................... 125
8.1.21 INTRPIN1—Interrupt Pin (D1:F0) ....................................................... 125
8.1.22 BCTRL1—Bridge Control (D1:F0) ...................................................... 126
8.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) .................. 128
7
DMIBAR Registers—Direct Media Interface (DMI) RCRB ............................................... 99
7.1
8
Host-PCI Express* Graphics Bridge Registers (D1:F0) ................................................. 109
8.1
Intel
®
82925X/82925XE MCH Datasheet
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