Stratix III Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SIII5V1-1.4
Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
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performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liabil-
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expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest ver-
sion of device specifications before relying on any published information and before placing orders for
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Contents
Chapter Revision Dates ......................................................................... xiii
About this Handbook .............................................................................. xv
How to Contact Altera ........................................................................................................................... xv
Typographic Conventions ..................................................................................................................... xv
Section I. Device Core
Chapter 1. Stratix III Device Family Overview
Introduction ............................................................................................................................................ 1–1
Features .............................................................................................................................................. 1–2
Architecture Features ............................................................................................................................ 1–5
Logic Array Blocks and Adaptive Logic Modules ...................................................................... 1–5
MultiTrack Interconnect .................................................................................................................. 1–6
TriMatrix Embedded Memory Blocks ........................................................................................... 1–7
DSP Blocks ......................................................................................................................................... 1–7
Clock Networks and PLLs .............................................................................................................. 1–8
I/O Banks and I/O Structure ......................................................................................................... 1–9
External Memory Interfaces ............................................................................................................ 1–9
High Speed Differential I/O Interfaces with DPA .................................................................... 1–10
Hot Socketing and Power-On Reset ............................................................................................ 1–10
Configuration .................................................................................................................................. 1–11
Remote System Upgrades ............................................................................................................. 1–12
IEEE 1149.1 (JTAG) Boundary Scan Testing ............................................................................... 1–12
Design Security ............................................................................................................................... 1–12
SEU Mitigation ................................................................................................................................ 1–13
Programmable Power .................................................................................................................... 1–13
Signal Integrity ............................................................................................................................... 1–14
Reference and Ordering Information ............................................................................................... 1–14
Software ........................................................................................................................................... 1–14
Ordering Information .................................................................................................................... 1–15
Referenced Documents ....................................................................................................................... 1–16
Document Revision History ............................................................................................................... 1–16
Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Introduction ............................................................................................................................................ 2–1
Logic Array Blocks ................................................................................................................................ 2–1
LAB Interconnects ............................................................................................................................ 2–3
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Contents
Stratix III Device Handbook, Volume 2
LAB Control Signals ......................................................................................................................... 2–4
Adaptive Logic Modules ...................................................................................................................... 2–5
ALM Operating Modes ................................................................................................................... 2–8
Register Chain ................................................................................................................................. 2–20
ALM Interconnects ......................................................................................................................... 2–22
Clear and Preset Logic Control .................................................................................................... 2–23
LAB Power Management Techniques ......................................................................................... 2–23
Conclusion ............................................................................................................................................ 2–24
Referenced Documents ....................................................................................................................... 2–24
Document Revision History ............................................................................................................... 2–24
Chapter 3. MultiTrack Interconnect in Stratix III Devices
Introduction ............................................................................................................................................ 3–1
Row Interconnects ................................................................................................................................. 3–1
Column Interconnects ........................................................................................................................... 3–3
Memory Block Interface ........................................................................................................................ 3–8
DSP Block Interface ............................................................................................................................. 3–10
I/O Block Connections to Interconnect ............................................................................................ 3–13
Conclusion ............................................................................................................................................ 3–14
Document Revision History ............................................................................................................... 3–15
Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices
Introduction ............................................................................................................................................ 4–1
Overview ................................................................................................................................................. 4–1
TriMatrix Memory Block Types ..................................................................................................... 4–3
Parity Bit Support ............................................................................................................................. 4–3
Byte Enable Support ........................................................................................................................ 4–3
Packed Mode Support ..................................................................................................................... 4–5
Address Clock Enable Support ...................................................................................................... 4–5
Mixed Width Support ...................................................................................................................... 4–7
Asynchronous Clear ........................................................................................................................ 4–7
Error Correction Code (ECC) Support .......................................................................................... 4–8
Memory Modes ...................................................................................................................................... 4–9
Single Port RAM ............................................................................................................................. 4–10
Simple Dual-Port Mode ................................................................................................................. 4–12
True Dual-Port Mode ..................................................................................................................... 4–15
Shift-Register Mode ....................................................................................................................... 4–17
ROM Mode ...................................................................................................................................... 4–18
FIFO Mode ....................................................................................................................................... 4–19
Clocking Modes ................................................................................................................................... 4–19
Independent Clock Mode .............................................................................................................. 4–19
Input/Output Clock Mode ........................................................................................................... 4–20
Read/Write Clock Mode ............................................................................................................... 4–20
Single Clock Mode ......................................................................................................................... 4–20
Design Considerations ........................................................................................................................ 4–20
Selecting TriMatrix Memory Blocks ............................................................................................ 4–20
Conflict Resolution ......................................................................................................................... 4–21
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Contents
Contents
Read During Write .........................................................................................................................
Power-Up Conditions and Memory Initialization ....................................................................
Power Management .......................................................................................................................
Conclusion ............................................................................................................................................
Document Revision History ...............................................................................................................
4–21
4–24
4–24
4–24
4–25
Chapter 5. DSP Blocks in Stratix III Devices
Introduction ............................................................................................................................................ 5–1
DSP Block Overview ............................................................................................................................. 5–1
Simplified DSP Operation .................................................................................................................... 5–3
Operational Modes Overview ............................................................................................................. 5–9
DSP Block Resource Descriptions ..................................................................................................... 5–10
Input Registers ................................................................................................................................ 5–11
Multiplier and First-Stage Adder ................................................................................................. 5–15
Pipeline Register Stage .................................................................................................................. 5–16
Second-Stage Adder ....................................................................................................................... 5–16
Round and Saturation Stage ......................................................................................................... 5–17
Second Adder and Output Registers ........................................................................................... 5–17
Operational Mode Descriptions ........................................................................................................ 5–18
Independent Multiplier Modes .................................................................................................... 5–18
9-, 12- and 18-Bit Multiplier .......................................................................................................... 5–18
36-Bit Multiplier ............................................................................................................................. 5–22
Double Multiplier ........................................................................................................................... 5–23
Two-Multiplier Adder Sum Mode ............................................................................................... 5–25
18 × 18 Complex Multiply ............................................................................................................. 5–29
Four-Multiplier Adder ................................................................................................................... 5–31
Multiply Accumulate Mode ......................................................................................................... 5–33
Shift Modes ...................................................................................................................................... 5–34
Rounding and Saturation Mode ................................................................................................... 5–36
DSP Block Control Signals ............................................................................................................ 5–39
Application Examples ......................................................................................................................... 5–41
FIR Example .................................................................................................................................... 5–41
FFT Example ................................................................................................................................... 5–48
Software Support ................................................................................................................................. 5–49
Conclusion ............................................................................................................................................ 5–49
Referenced Documents ....................................................................................................................... 5–49
Document Revision History ............................................................................................................... 5–50
Chapter 6. Clock Networks and PLLs in Stratix III Devices
Introduction ............................................................................................................................................ 6–1
Clock Networks in Stratix III Devices ................................................................................................. 6–1
Clock Input Connections to PLLs ................................................................................................ 6–12
Clock Output Connections ............................................................................................................ 6–13
Clock Source Control for PLLs ..................................................................................................... 6–14
Clock Control Block ....................................................................................................................... 6–16
Clock Enable Signals ...................................................................................................................... 6–20
PLLs in Stratix III Devices .................................................................................................................. 6–22
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