P ro du ct O ve rvi ew , DS 2, D ec . 20 02
TE 3- F A L C
T3 /E 3 Fr a m er & L i n e In te r f ac e f o r
A T M , F r am e R el a y & P P P /I P
P EF 3 46 0 E , V e r s io n 1 .2
W ir ed
Co m mu n ic a ti o n s
N e v e r
s t o p
t h i n k i n g .
Product Overview
Revision History:
Previous Version:
Page
2002-12-10
Product Overview , DS1, 2002-01-24
DS2
Subjects (major changes since last revision)
The information in this document is subject to change without notice.
Edition 2002-12-10
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©
Infineon Technologies AG 2002.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide
(www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TE3-FALC
PEF 3460 E
Table of Contents
1
1.1
1.2
1.3
1.4
2
2.1
3
3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.3
3.2.4
3.2.4.1
3.2.4.2
3.2.4.3
3.2.5
3.2.5.1
3.2.6
3.2.7
3.2.7.1
3.2.7.2
3.2.8
3.2.8.1
3.2.8.2
3.2.9
3.2.10
3.2.11
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
Page
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimum System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog T3/E3 Line Interface Unit (LIU) . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Attenuator (DJAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive DJAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit DJAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Center/Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rx and Tx Jitter Attenuator Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alarm Indication Signal (AIS), Idle Signal . . . . . . . . . . . . . . . . . . . . .
Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3/E3 Bit Error Rate Test (BERT) Unit . . . . . . . . . . . . . . . . . . . . . . . .
ATM Cell Processor and PLCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCP Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC Packet Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPP Header Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Core with Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Interface Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T3/E3 Analog Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Analog LOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
16
16
17
17
17
17
18
18
18
19
19
19
19
20
20
20
20
21
21
21
22
22
23
23
24
24
26
26
26
26
27
27
27
28
Product Overview
DS2, 2002-12-10
TE3-FALC
PEF 3460 E
Table of Contents
4.1.7
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.7
4.8
4.9
4.10
4.11
5
5.1
5.2
6
7
7.1
7.2
Page
28
29
29
29
30
31
31
32
32
33
33
33
33
33
34
34
Transmit Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3/E3 Digital Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3/E3 Overhead, Bitstream and Payload Access Interface . . . . . . . . . .
Clock Multiplier Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Interface (UTOPIA / POS-PHY / UTOPIA-L2X) . . . . . . . . . . . . . .
UTOPIA Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POS-PHY Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA-L2X Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Accesses (Device Configuration/Control) . . . . . . . . . . . . . . . . . .
Master Accesses (8-Bit EPROM Load Function) . . . . . . . . . . . . . . . . . .
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS and TEST Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Tools and Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Product Overview
4
DS2, 2002-12-10
TE3-FALC
PEF 3460 E
Overview
1
Overview
This Product Overview provides an overview about the functionality of the "T3/E3
Framer & Line Interface for ATM, Frame Relay & PPP/IP" TE3-FALC (PEF 3460 E).
Note: Some features mentioned in this document are options for future firmware
enhancements and not supported with the current release of firmware. These
options are marked with a preceding " " symbol.
The TE3-FALC is a complete solution for a T3/E3 broadband interface. It includes DS3/
E3 framing, analog line interface, two jitter attenuators and the mapping of ATM or
HDLC-framed PPP. The TE3-FALC also integrates a microcontroller which handles the
device configuration, processes alarms and gathers statistics in accordance with the
relevant managed MIB objects. A firmware image needs to be uploaded as part of the
initialization of the device.
On line side the TE3-FALC interfaces to a 75 ohm co-axial cable via transformers. Highly
accurate analog pulse shaping removes the need to measure cable length and set the
Line Build Out.
On the system side, industry standard UTOPIA and POS-PHY interface as well as
UTOPIA-L2X and serial clock/data port are provided. This allows the TE3-FALC to be
connected to a wide array of Layer 2/3 & 4 network processors.
Product Overview
5
DS2, 2002-12-10
京公网安备 11010802033920号
EEWORLD
