STT3463P
Elektronische Bauelemente
-3 A, -60 V, R
DS(ON)
155 m
P-Channel Enhancement Mode MOSFET
RoHS Compliant Product
A suffix of “-C” specifies halogen and lead-free
DESCRIPTION
These miniature surface mount MOSFETs utilize
a high cell density process. Low R
DS(on)
assures minimal
power loss and conserves energy, making this device
ideal for use in power management circuitry.
A
E
6
5
4
TSOP-6
L
FEATURES
B
Low R
DS(on)
provides higher efficiency and extends
battery life.
Miniature TSOP-6 surface mount package saves
board space.
High power and current handling capability.
Extended V
GS
range (±25) for battery pack
applications.
F
DG
1
2
3
C
K
H
J
REF.
A
B
C
D
E
F
APPLICATION
PWMDC-DC converters, power management
in portable and battery-powered products such as computers,
printers, battery charger, telecommunication power system,
and telephones power system.
D
Millimeter
Min.
Max.
2.70
3.10
2.60
3.00
1.40
1.80
1.10 MAX.
1.90 REF.
0.30
0.50
REF.
G
H
J
K
L
Millimeter
Min.
Max.
0
0.10
0.60 REF.
0.12 REF.
0°
10°
0.95 REF.
D
PACKAGE INFORMATION
Package
TSOP-6
MPQ
3K
Leader Size
7’ inch
D
D
G
S
ABSOLUTE MAXIMUM RATINGS
(T
A
=25°C unless otherwise specified)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
1
Pulsed Drain Current
2
Continuous Source Current (Diode Conduction)
1
Power Dissipation
1
Operating Junction and Storage Temperature Range
T
A
= 25
°C
T
A
= 70
°C
T
A
= 25
°C
T
A
= 70
°C
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
Tj, Tstg
Ratings
-60
±20
-3.0
-2.4
-15
-1.7
2.0
1.3
-55 ~ 150
Unit
V
V
A
A
A
W
°C
Thermal Resistance Ratings
Maximum Junction to Ambient
1
t
≦
5 sec
R
JA
62.5
110
°C
/ W
Notes:
1. Surface Mounted on 1” x 1” FR4 Board.
2. Pulse width limited by maximum junction temperature.
http://www.SeCoSGmbH.com/
Any changes of specification will not be informed individually.
08-Apr-2011 Rev. A
Page 1 of 2
STT3463P
Elektronische Bauelemente
-3 A, -60 V, R
DS(ON)
155 m
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Gate-Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
1
Drain-Source On-Resistance
1
Forward Transconductance
1
Diode Forward Voltage
Symbol
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(ON)
g
fs
V
SD
Min.
-1
-
-
-
-20
-
-
-
-
Typ.
-
-
-
-
-
-
-
8
-
Max.
-
±100
-1
-10
-
155
230
-
-1.2
Unit
V
nA
μA
A
mΩ
S
V
Test Conditions
V
DS
= V
GS
, I
D
= -250μA
V
DS
=0, V
GS
= ±20V
V
DS
= -48V, V
GS
=0
V
DS
= -48V, V
GS
=0, T
J
= 55°C
V
DS
= -5V, V
GS
= -10V
V
GS
= -10V, I
D
= -3A
V
GS
= -4.5V, I
D
= -2.5A
V
DS
= -15V, I
D
= -3.0A
I
S
= -2.5A, V
GS
=0
Static
Dynamic
2
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Q
g
Q
gs
Q
gd
T
d(on)
T
r
T
d(off)
T
f
-
-
-
-
-
-
-
18
5
2
8
10
35
12
-
-
-
-
-
-
-
nS
nC
V
DS
= -30V,
V
GS
= -4.5V,
I
D
= -3A
V
DD
= -30V,
V
GEN
= -10V,
R
L
=30Ω,
I
D
= -1A,
R
G
=6Ω
Notes:
1. Pulse test：PW
≦
300 us duty cycle
≦
2%.
2. Guaranteed by design, not subject to production testing.
http://www.SeCoSGmbH.com/
Any changes of specification will not be informed individually.
08-Apr-2011 Rev. A
Page 2 of 2
Embedded System
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