K7A163630B
K7A161830B
512Kx36 & 1Mx18 Synchronous SRAM
18Mb Sync. Pipelined Burst SRAM
Specification
100TQFP with Pb / Pb-Free
(RoHS compliant)
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 3.0 April 2006
K7A163630B
K7A161830B
Document Title
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
History
1. Initial draft
1. Update the DC current spec(I
CC
, I
SB
)
1. Change the ISB,ISB1,ISB2
- ISB ; from 120mA to 170mA
- ISB1 ; from 80mA to 150mA
- ISB2 ; from 80mA to 130mA
1. Remove the 1.8V Vdd Voltage level
1. Remove the -14 speed bin
1. Finalize the datasheet
1. Add the overshoot timing
1. Change ordering information
Draft Date
Mar. 22. 2004
May. 21. 2004
Sep. 21. 2004
Remark
Advance
Preliminary
Preliminary
0.3
0.4
1.0
2.0
3.0
Oct. 18. 2004
Jan. 04. 2005
July 18. 2005
Feb. 16. 2006
Apr. 03. 2006
Preliminary
Preliminary
Final
Final
Final
-2-
Rev. 3.0 April 2006
K7A163630B
K7A161830B
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 2.5 or 3.3V +/- 5% Power Supply.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A (Lead and Lead free package)
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A163630B and K7A161830B are 18,874,368-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
It is organized as 512K(1M) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor (ADSP) or address status cache controller
(ADSC) inputs. Subsequent burst addresses are generated
internally in the system′s burst sequence and are con-
trolled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence
(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A163630B and K7A161830B are fabricated using
SAMSUNG′s high performance CMOS technology and is
available in a 100pin TQFP. Multiple power and ground
pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
t
CYC
t
CD
t
OE
-25
4.0
2.6
2.6
-16
6.0
3.5
3.5
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
18
or A
0
~A
19
ADDRESS
REGISTER
512Kx36, 1Mx18
MEMORY
ARRAY
A′
0
~A′
1
A
2
~A
18
or A
2
~A
19
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
DQPa ~ DQPd
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Rev. 3.0 April 2006
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