ADVANCE INFORMATION
Am29LV128M
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit 3.0 Volt-only
Uniform Sector Flash Memory with Enhanced VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Single power supply operation
— 3 volt read, erase, and program operations
■
Enhanced VersatileI/O control
— Device generates and tolerates voltages on all I/Os
and control inputs as determined by the voltage on the
V
IO
pin; operates from 1.65 to 3.6 V (see page 8)
■
Manufactured on 0.23 µm MirrorBit process
technology
■
SecSi (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
■
Flexible sector architecture
— Two hundred fifty-six 32 Kword (64 Kbyte) sectors
■
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
■
Minimum 100,000 erase cycle guarantee per sector
■
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■
High performance
— 90 ns access time
— 25 ns page read times
— 0.4 s typical sector erase time
— 5.9 µs typical write buffer word programming time:
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
■
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
■
Package options
— 56-pin TSOP
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■
Hardware features
— Sector Protection: hardware-level method of
preventing write operations within a sector
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
25270
Rev:
B
Amendment/0
Issue Date:
July 1, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV128M is a 128 Mbit, 3.0 volt single power
supply flash memory devices organized as 8,388,608
words or 16,777,216 bytes. The device has a 16-bit
wide data bus that can also function as an 8-bit wide
data bus by using the BYTE# input. The device can be
programmed either in the host system or in standard
EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
CC
) and an I/O voltage range (V
IO
), as
specified in the
Product Selector Guide
and the
Order-
ing Information
sections. The device is offered in a
56-pin TSOP or 64-ball Fortified BGA package. Each
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(WP#/ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or
monitor the
Ready/Busy# (RY/BY#)
output to deter-
mine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The
Enhanced VersatileI/O™
(V
IO
) control allows the
host system to set the voltage levels that the device
generates and tolerates on all I/Os and control inputs
to the same voltage level that is asserted on the V
IO
pin. This allows the device to operate in a 1.8 V or 3 V
system environment as required.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The
Program
Suspend/Program Resume
feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power c ons umption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi (Secured Silicon) Sector
provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
The
Write Protect (WP#/ACC)
feature protects the
first or last sector by asserting a logic low on the WP#
pin.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
www.amd.com
→
Flash Memory
→
Product Informa-
tion
→
MirrorBit
→
Flash Information
→
Technical Docu-
mentation.
The following is a partial list of documents
closely related to this product:
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
Am29LV256M, 256 Mbit MirrorBit Flash device
(in 64-ball, 18 x 12 mm Fortified BGA package)
2
Am29LV128M
July 1, 2002
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Special Package Handling Instructions .................................... 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations ....................................................... 9
Figure 6. Erase Operation .............................................................. 32
Command Definitions ............................................................. 33
Table 9. Command Definitions (x16 Mode, BYTE# = V
IH
) ............. 33
Table 10. Command Definitions (x8 Mode, BYTE# = V
IL
).............. 34
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 35
DQ7: Data# Polling ................................................................. 35
Figure 7. Data# Polling Algorithm .................................................. 35
RY/BY#: Ready/Busy# ............................................................ 36
DQ6: Toggle Bit I .................................................................... 36
Figure 8. Toggle Bit Algorithm ........................................................ 37
Word/Byte Configuration .......................................................... 9
Enhanced VersatileIO (V
IO
) Control ...................................... 9
Requirements for Reading Array Data ................................... 10
Page Mode Read ............................................................................10
Writing Commands/Command Sequences ............................ 10
Write Buffer .....................................................................................10
Accelerated Program Operation ......................................................10
Autoselect Functions .......................................................................10
DQ2: Toggle Bit II ................................................................... 37
Reading Toggle Bits DQ6/DQ2 ............................................... 37
DQ5: Exceeded Timing Limits ................................................ 38
DQ3: Sector Erase Timer ....................................................... 38
DQ1: Write-to-Buffer Abort ..................................................... 38
Table 11. Write Operation Status................................................... 38
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 39
Figure 9. Maximum Negative Overshoot Waveform ..................... 39
Figure 10. Maximum Positive Overshoot Waveform ..................... 39
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table........................................................ 12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Test Setup .................................................................... 41
Table 12. Test Specifications ......................................................... 41
Autoselect Mode ..................................................................... 18
Table 3. Autoselect Codes, (High Voltage Method) ....................... 18
Sector Protection and Unprotection ........................................ 18
Write Protect (WP#) ................................................................ 19
Temporary Sector Unprotect .................................................. 19
Figure 1. Temporary Sector Unprotect Operation ...........................19
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...20
Key to Switching Waveforms. . . . . . . . . . . . . . . . 41
Figure 12. Input Waveforms and
Measurement Levels ...................................................................... 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Read-Only Operations ........................................................... 42
Figure 13. Read Operation Timings ............................................... 42
Figure 14. Page Read Timings ...................................................... 43
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Table 4. SecSi Sector Contents ...................................................... 21
Hardware Data Protection ...................................................... 21
Low VCC Write Inhibit .....................................................................21
Write Pulse “Glitch” Protection ........................................................22
Logical Inhibit ..................................................................................22
Power-Up Write Inhibit ....................................................................22
Hardware Reset (RESET#) .................................................... 44
Figure 15. Reset Timings ............................................................... 44
Erase and Program Operations .............................................. 45
Figure 16. Program Operation Timings .......................................... 46
Figure 17. Accelerated Program Timing Diagram .......................... 46
Figure 18. Chip/Sector Erase Operation Timings .......................... 47
Figure 19. Data# Polling Timings (During Embedded Algorithms) . 48
Figure 20. Toggle Bit Timings (During Embedded Algorithms) ...... 49
Figure 21. DQ2 vs. DQ6 ................................................................. 49
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 5. CFI Query Identification String ..........................................22
Table 6. System Interface String..................................................... 23
Table 7. Device Geometry Definition ..............................................23
Table 8. Primary Vendor-Specific Extended Query ........................24
Temporary Sector Unprotect .................................................. 50
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 50
Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 51
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................ 24
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25
Word/Byte Program Command Sequence ............................. 25
Unlock Bypass Command Sequence ..............................................26
Write Buffer Programming ...............................................................26
Accelerated Program ......................................................................27
Figure 3. Write Buffer Programming Operation ...............................28
Figure 4. Program Operation ..........................................................29
Alternate CE# Controlled Erase and Program Operations ..... 52
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .......................................................................... 53
Program Suspend/Program Resume Command Sequence ... 29
Figure 5. Program Suspend/Program Resume ...............................30
Chip Erase Command Sequence ........................................... 30
Sector Erase Command Sequence ........................................ 30
Erase Suspend/Erase Resume Commands ........................... 31
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 53
Erase And Programming Performance. . . . . . . . 54
TSOP Pin and BGA Package Capacitance . . . . . 54
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 55
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline
Package (TSOP) ..................................................................... 55
LAA064—64-Ball Fortified Ball Grid Array
13 x 11 mm Package .............................................................. 56
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 57
July 1, 2002
Am29LV128M
3
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Regulated Voltage Range
V
CC
= 3.0–3.6 V
Full Voltage Range
V
CC
= 2.7–3.6 V
V
IO
= 3.0–3.6 V
V
IO
= 1.65–1.95 V
V
IO
= 2.7–3.6 V
V
IO
= 1.65–1.95 V
90
90
25
25
94R
99R
104
109
100
100
30
30
114
119
110
110
40
40
124
129
120
120
40
40
Am29LV128M
Speed/
Voltage
Option
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time (t
PACC
)
Max. OE# Access Time (ns)
Note:
See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
V
IO
RESET#
WE#
WP#/ACC
BYTE#
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ0
–
DQ15 (A-1)
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A22–A0
4
Am29LV128M
July 1, 2002
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
NC
V
IO
56-Pin Standard TSOP
NC
NC
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
NC
V
IO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin Reverse TSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
July 1, 2002
Am29LV128M
5
FPGA/CPLD
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