USP1H2R2MDD1CV datasheet, PDF - EEWORLD Datasheet

USP1H2R2MDD1CV: DescriptionAluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 50V, 20% +Tol, 20% -Tol, 2.2uF, Through Hole Mount, 7 MML RADIAL LEADED; CategoryPassive components capacitor; File Size88KB，1 Pages; ManufacturerNichicon; Websitehttp://www.nichicon.co.jp; Environmental Compliance

Download Datasheet Parametric View All

USP1H2R2MDD1CV Overview

Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 50V, 20% +Tol, 20% -Tol, 2.2uF, Through Hole Mount, 7 MML RADIAL LEADED

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Nichicon
package instruction	,
Reach Compliance Code	compliant
ECCN code	EAR99
capacitance	2.2 µF
Capacitor type	ALUMINUM ELECTROLYTIC CAPACITOR
diameter	4 mm
dielectric materials	ALUMINUM (WET)
JESD-609 code	e3
leakage current	0.01 mA
length	7 mm
Manufacturer's serial number	SP
Installation features	THROUGH HOLE MOUNT
negative tolerance	20%
Number of terminals	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package shape	CYLINDRICAL PACKAGE
Package form	Radial
method of packing	Bulk
polarity	NON-POLARIZED
positive tolerance	20%
Rated (DC) voltage (URdc)	50 V
ripple current	14 mA
series	SP
surface mount	NO
Delta tangent	0.12
Terminal surface	Matte Tin (Sn)
Terminal pitch	1.5 mm
Terminal shape	WIRE

Questions + Reading "MCU Engineer Training Record" Questions: Fortunately, I got a copy of "MCU Engineer Training Record". Chapter 1 1.1 Turning iPhone into an electrocardiograph is very interesting. The right channel is used as the power output of the MSP430 sy...; dlyt03 Microcontroller MCU

Confusion in the process of learning FPGA: I just started to learn FPGA. I have been reading forums for a long time, and I have also learned Verilog. I have tried to learn how to use Quartus II and ModelSim. But I still feel that I have not ma...; 奔跑的蜗牛 FPGA/CPLD

Realization of high-speed serial communication between DSP and PC: UART is used to solve the rate matching problem between DSP and PC, and a specific implementation circuit is given. Keywords: DSP UART serial communication FIFO DSP is a microprocessor chip specially ...; iiyuyu DSP and ARM Processors

【Signal Processing】Real-time infrared image processing system based on DSP+FPGA+ASIC: With the rapid development of infrared focal plane array technology, infrared imaging systems have achieved high frame rate, high resolution, high reliability and miniaturization. They have been incre...; hangsky FPGA/CPLD

Transmitting FSK modulated signal generated by DSP: [i=s] This post was last edited by paulhyde on 2014-9-15 09:23 [/i] The frequency of the modulated signal I generate is 150K. Can it be directly inductively coupled through a power amplifier without m...; hpfei77 Electronics Design Contest

Recruiting drive engineers: Job title: Driver Engineer Job requirements: 1. Bachelor degree or above in electronics, communications, computers, automatic control and related majors; 2. More than 1 year of embedded product develo...; 之城 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components