PBSS4041SN
60 V, 6.7 A NPN/NPN low V
CEsat
(BISS) transistor
Rev. 2 — 18 October 2010
Product data sheet
1. Product profile
1.1 General description
NPN/NPN low V
CEsat
Breakthrough In Small Signal (BISS) transistor in a SOT96-1 (SO8)
medium power Surface-Mounted Device (SMD) plastic package.
Table 1.
Product overview
Package
NXP
PBSS4041SN
SOT96-1
Name
SO8
PNP/PNP
complement
PBSS4041SP
NPN/PNP
complement
PBSS4041SPN
Type number
1.2 Features and benefits
Very low collector-emitter saturation voltage V
CEsat
High collector current capability I
C
and I
CM
High collector current gain (h
FE
) at high I
C
High efficiency due to less heat generation
Smaller required Printed-Circuit Board (PCB) area than for conventional transistors
1.3 Applications
Loadswitch
Battery-driven devices
Power management
Charging circuits
Power switches (e.g. motors, fans)
1.4 Quick reference data
Table 2.
V
CEO
I
C
I
CM
R
CEsat
[1]
Quick reference data
Conditions
open base
single pulse;
t
p
≤
1 ms
I
C
= 4 A; I
B
= 0.2 A
[1]
Symbol Parameter
collector-emitter voltage
collector current
peak collector current
collector-emitter
saturation resistance
Min
-
-
-
-
Typ
-
-
-
32
Max
60
6.7
15
48
Unit
V
A
A
mΩ
Pulse test: t
p
≤
300
μs; δ ≤
0.02.
NXP Semiconductors
PBSS4041SN
60 V, 6.7 A NPN/NPN low V
CEsat
(BISS) transistor
2. Pinning information
Table 3.
Pin
1
2
3
4
5
6
7
8
Pinning
Description
emitter TR1
base TR1
emitter TR2
TR1
TR2
Simplified outline
8
5
Graphic symbol
8
7
6
5
base TR2
collector TR2
collector TR2
collector TR1
collector TR1
1
4
1
2
3
4
006aaa966
3. Ordering information
Table 4.
Ordering information
Package
Name
PBSS4041SN
SO8
Description
Version
plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Type number
4. Marking
Table 5.
Marking codes
Marking code
4041SN
Type number
PBSS4041SN
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
I
C
I
CM
I
B
P
tot
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
collector current
peak collector current
base current
total power dissipation
T
amb
≤
25
°C
[1]
[2]
[3]
Conditions
open emitter
open base
open collector
single pulse;
t
p
≤
1 ms
Min
-
-
-
-
-
-
-
-
-
Max
60
60
5
6.7
15
1
0.73
1
1.7
Unit
V
V
V
A
A
A
W
W
W
Per transistor
PBSS4041SN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 18 October 2010
2 of 15
NXP Semiconductors
PBSS4041SN
60 V, 6.7 A NPN/NPN low V
CEsat
(BISS) transistor
Table 6.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Per device
P
tot
total power dissipation
T
amb
≤
25
°C
[1]
[2]
[3]
Parameter
Conditions
Min
-
-
-
-
−55
−65
Max
0.86
1.4
2.3
150
+150
+150
Unit
W
W
W
°C
°C
°C
T
j
T
amb
T
stg
[1]
[2]
[3]
junction temperature
ambient temperature
storage temperature
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm
2
.
Device mounted on a ceramic PCB, Al
2
O
3
, standard footprint.
3.0
P
tot
(W)
2.0
006aac322
(1)
(2)
1.0
(3)
0.0
−75
−25
25
75
125
175
T
amb
(°C)
(1) Ceramic PCB, Al
2
O
3
, standard footprint
(2) FR4 PCB, mounting pad for collector 1 cm
2
(3) FR4 PCB, standard footprint
Fig 1.
Per device: Power derating curves
PBSS4041SN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 18 October 2010
3 of 15
NXP Semiconductors
PBSS4041SN
60 V, 6.7 A NPN/NPN low V
CEsat
(BISS) transistor
6. Thermal characteristics
Table 7.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to ambient
Conditions
in free air
[1]
[2]
[3]
Min
-
-
-
-
Typ
-
-
-
-
Max
170
125
75
40
Unit
K/W
K/W
K/W
K/W
Per transistor
R
th(j-sp)
Per device
R
th(j-a)
thermal resistance from
junction to solder point
thermal resistance from
junction to ambient
in free air
[1]
[2]
[3]
-
-
-
-
-
-
145
90
55
K/W
K/W
K/W
[1]
[2]
[3]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm
2
.
Device mounted on a ceramic PCB, Al
2
O
3
, standard footprint.
10
3
Z
th(j-a)
(K/W)
10
2
duty cycle = 1
0.75
0.33
0.2
0.1
10
0.02
1
0.05
0.01
0.5
006aac323
0
10
−1
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 2.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
PBSS4041SN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 18 October 2010
4 of 15
NXP Semiconductors
PBSS4041SN
60 V, 6.7 A NPN/NPN low V
CEsat
(BISS) transistor
10
3
Z
th(j-a)
(K/W)
duty cycle = 1
10
2
0.75
0.33
0.2
10
0.1
0.05
0.02
1
0
0.01
0.5
006aac324
10
−1
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, mounting pad for collector 1 cm
2
Fig 3.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aac325
10
2
Z
th(j-a)
(K/W)
10
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
1
0
10
−1
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
10
2
t
p
(s)
10
3
Ceramic PCB, Al
2
O
3
, standard footprint
Fig 4.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
PBSS4041SN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 18 October 2010
5 of 15
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