Configurable VT/TU slot selection for DS1, E1, and
J1 insertion and drop.
Automatic receive monitor functions include VT/TU
RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
Complies with GR-253-CORE, GR-499, ITU-T
G.707, G.704, G.783, T1.105, JT-G707, ETS 300
417-1-1.
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1.8 Jitter Attenuation
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PLL-free receive operation using built-in digital jitter
attenuator (in VT/VC mode or M13 mode).
Configurable to meet jitter and MTIE requirements.
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1.9 PDH Interfaces
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One DS3, 7x DS2.
x28/x21 framed or unframed DS1 or E1 interfaces.
One additional dedicated protection channel for
DS2/DS1/E1.
1.6 M13 Features
s
Configurable multiplexer/demultiplexer for 28 DS1
signals, 21 E1 signals, or 7 DS2 signals to/from a
DS3 signal.
Operates in either M23 or C-bit parity mode.
Provisionable time slot selection for DS1, E1, and
DS2 insertion or drop.
Full alarm monitoring and generation (LOS, BPV,
EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit par-
ity errors, FEBE).
HDLC transmitter with 128-byte data buffer and
HDLC receiver with 128-byte data FIFO for the C-bit
parity path maintenance data link.
DS3, DS2, DS1, and E1 loopback and loopback
request generation.
Complies with T1.102, T1.107, T1.231, T1.403,
T1.404, GR 499, G.747, and G.775.
1.10 T1/E1/J1 Framing Features (x28/x21)
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x28/x21 T1/E1/J1 channels.
Line coding: B8ZS, HDB3, ZCS, AMI, and
CMI (JJ20-11).
T1 framing modes: ESF, D4,
SLC
®
-96, T1 DM DDS,
and SF (F
t
only).
E1 framing: G.704 basic and CRC-4 multiframe con-
sistent with G.706.
J1 framing modes: JESF (Japan).
Supports T1 and E1 unframed and transparent trans-
mission format.
T1 signaling modes: transparent;
register and system access for ESF 2-state, 4-state,
and 16-state; D4 2-state, 4-state, and 16-state;
SLC-96
2-state, 4-state, and 16-state; J-ESF han-
dling groups maintenance and signaling; VT 1.5
SPE 2, 4, 16 state.
E1 signaling modes: transparent;
register and system access for entire TS16 multi-
frame structure as per ITU G.732.
Signaling debounce and change of state interrupt.
V5.2 Sa7 processing.
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1.7 DS3/DS2/DS1/E1 Cross Connect
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Highly configurable interconnect for up to 28 DS1 or
21 E1 signals to/from the framer, external pins, M13,
or VT mappers.
Supports up to seven DS2 signals to/from the exter-
nal pins or M13.
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2
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1.11 System Test and Maintenance
s
1 Features
(continued)
s
Alarm reporting and performance monitoring per
AT&T,
ANSI,
ITU-T, and ETSI standards.
Facility data link features:
— HDLC or transparent access for either ESF or
DDS + FDL frame formats.
— Register/stack access for
SLC-96
transmit and re-
ceive data.
— Extended superframe (ESF): automatic transmis-
sion of the ESF performance report messages
(PRM). Automatic transmission of the
ANSI
T1.403 ESF performance report messages. Auto-
matic detection and transmission of the
ANSI
T1.403 ESF FDL bit-oriented codes.
— Register/stack access for all CEPT Sa-bits trans-
mit and receive data.
HDLC features:
— HDLC or transparent mode.
— Programmable logical channel assignment: any
time slot, any bit for ISDN D-channel, also inserts/
extracts C-channels for V5.1, V5.2 interfaces.
— 64 logical channels in both transmit and receive di-
rection (any framing format).
— Maximum channel data rate: 64 kbits/s.
— Minimum channel data rate: 4 kbits/s (DS1-FDL or
E1 Sa bit).
— 128-byte FIFO per channel in both transmit and re-
ceive direction.
— Tx to Rx loopback supported.
System interfaces:
— Concentration highway interface: Single clock and
frame sync signals; programmable clock rates at
2.048 MHz, 4.096 MHz, 8.192 MHz, and
16.384 MHz; programmable data rates at 2.048
Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s; programmable
clock edges and bit/byte offsets.
— Parallel system bus interface at 19.44 MHz for
data and signaling: single clock and frame sync
signals.
— Time-division multiplex data rate serial interface at
1.544 MHz or 2.048 MHz. Twenty-eight receive
data, clock, and frame sync signals. Twenty-eight
transmit data signals with a global clock and frame
sync.
— Network serial multiplexed interface minimal pin
count serial interface at 51.84 MHz optimized for
data and IMA applications.
A variety of loopback modes implemented on
SONET/SDH side as well as on framer level.
Built-in test pattern generator and monitor config-
urable for simultaneously testing E1, DS1, DS2, and
DS3 (one channel each).
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Microprocessor Interface
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20-bit address and 16-bit data interface with 16 MHz
to 66 MHz read and write access.
Compatible with most industry-standard processors.
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s
Chip Testing and Maintenance
s
IEEE
* 1149.1 JTAG boundary scan.
Interface to Other
Agere
ME Devices
Seamless interface to the following
Agere Systems’
devices:
s
TADM042G5.
s
*
IEEE
is a registered trademark of the Institute of Electrical and
Electronics Engineers, Inc.
Agere Systems Inc.
3
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
Table of Contents
By Major Sections
Contents
Page
Features ...................................................................................................................................................................1
Pin Information .......................................................................................................................................................8
Ordering Information ............................................................................................................................................ 61
Change History .................................................................................................................................................. 604
4
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Product Description
2 Preface
Table of Contents
Contents
Page
1 Features ............................................................................................................................................................... 1
1.6 M13 Features ................................................................................................................................................. 2
1.10 T1/E1/J1 Framing Features (x28/x21) ......................................................................................................... 2
1.11 System Test and Maintenance .................................................................................................................... 3
2.1 Major Categories ............................................................................................................................................ 6
2.2 Naming Convention for Registers and Parameters ....................................................................................... 6
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Embedded System
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