The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including
Pentium
TM
, PowerPC
TM
, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
operation without sacrificing performance or operating margins.
The device enters
standby mode
when
CE
is high. CMOS standby mode consumes
≤11
mW. Normal operation offers 75%
power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns
are ideal for high-performance applications. The chip enable (
CE
) input permits easy memory expansion with multiple-bank
memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (
CE
) and output enable (
OE
) LOW, with write enable (
WE
) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged
in high volume industry standard packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
Max
+7.0
V
CC
+ 0.5
1.0
+150
+125
20
Unit
V
V
W
o
C
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
High Z
High Z
D
OUT
D
IN
Data
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
Key:
X = Don’t care, L = Low, H = High
9/24/04; v.1.2
Alliance Semiconductor
P. 2 of 9
AS7C256A
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
commercial
industrial
Symbol
V
CC
V
IH**
V
IL*
T
A
T
A
Min
4.5
2.2
-0.5
0
–40
Typical
5.0
–
–
–
–
Max
5.5
V
CC
+0.5
0.8
70
85
Unit
V
V
V
o
C
o
C
*
V
IL
min = –1.0V for pulse width less than 5ns.
**
V
IH
max = V
CC
+ 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)
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FPGA/CPLD
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