AS7C33128PFD32B datasheet, PDF

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AS7C33128PFD32B: Description3.3V 128K X 32/36 pipeline burst synchronous SRAM; File Size532KB，19 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS7C33128PFD32B Overview

3.3V 128K X 32/36 pipeline burst synchronous SRAM

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February 2005

AS7C33128PFD32B

AS7C33128PFD36B

3.3V 128K X 32/36 pipeline burst synchronous SRAM

Features

•

Organization: 131,072 words × 32 or 36 bits

Fast clock speeds to 200 MHz

Fast clock to data access: 3.0/3.5/4.0 ns

Fast OE access time: 3.0/3.5/4.0 ns

Fully synchronous register-to-register operation

Double-cycle deselect

Asynchronous output enable control

Available in 100-pin TQFP package

•

Individual byte write and global write

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Linear or interleaved burst control

Snooze mode for reduced power-standby

Common data inputs and data outputs

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[16:0]

CLK

CLR

Address

CLK

Burst logic

128K × 32/36

Memory

array

GWE

BWE

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

Power

down

Enable

delay

CLK

36/32

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

36/32

DQ [a:d]

Selection guide

–200

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

200

3.0

375

130

–166

166

3.5

350

100

–133

7.5

133

325

Units

MHz

1/31/05; v.1.1

Alliance Semiconductor

P. 1 of 19

AS7C33128PFD32B

AS7C33128PFD36B

Functional description

The AS7C33128PFD32B and AS7C33128PFD36B are high-performance CMOS 4-Mbit synchronous Static Random Access

Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline

for highest frequency on any given technology.

Timing for these devices is compatible with existing Pentium

synchronous cache specifications. This architecture is suited

for ASIC, DSP and PowerPC

™1

-based systems in computing, datacom, instrumentation, and telecommunications systems.

Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t

) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus

frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the

controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent

internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip

address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In

a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are

carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock

edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next

access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the LBO

input. With LBO unconnected or driven High, burst operations use a Pentium

count sequence. With LBO driven LOW, the

device uses a linear count sequence suitable for PowerPC

™

and many other applications.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable

GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more

bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are

disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled

Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low. This device operates in

double-cycle deselect feature during read cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC

and ADSP are as follows:

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).

• Master chip enable CE0 blocks ADSP, but not ADSC.

AS7C33128PFD32B and AS7C33128PFD36B family operates from a core 3.3V power supply. I/Os use a separate power

supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package

TQFP capacitance

Parameter

Input capacitance

I/O capacitance

* Guaranteed not tested

Symbol

IN*

I/O*

Test conditions

= 0V

OUT

= 0V

Min

Max

Unit

TQFP thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

1–layer

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

4–layer

Symbol

Typical

Units

°C/W

1 PowerPC

™

is a trademark International Business Machines Corporation.

1/31/05; v.1.1

Alliance Semiconductor

P. 4 of 19

AS7C33128PFD32B Related Products

	AS7C33128PFD32B	AS7C33128PFD36B-133TQCN
Description	3.3V 128K X 32/36 pipeline burst synchronous SRAM	3.3V 128K X 32/36 pipeline burst synchronous SRAM

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