PIC18F87K90 FAMILY
PIC18F87K90 Family
Silicon Errata and Data Sheet Clarification
The PIC18F87K90 family devices that you have
received conform functionally to the current Device Data
Sheet (DS39957D), except for the anomalies described
in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18F87K90 family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2
apply to the current silicon revision
(B5,
C6).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select
Programmer >
Reconnect.
b) For MPLAB X IDE, select
Window >
Dashboard
and click the
Refresh Debug
Tool Status
icon (
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
5.
Data Sheet clarifications and corrections start on
page
10,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC18F87K90
silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device
ID
(1)
524h
520h
52Ah
526h
510h
514h
3h
4h
5h
6h
10h
11h
12h
13h
Revision ID for Silicon Revision
(2)
A3
B1
B3
B5
C1
C3
C5
C6
Part Number
PIC18F65K90
PIC18F66K90
PIC18F85K90
PIC18F86K90
PIC18F67K90
PIC18F87K90
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of Configuration memory
space. They are shown in hexadecimal in the format “DEVID DEVREV”.
1:
Refer to the
“PIC18F6XKXX/8XKXX Family Flash Microcontroller Programming Specification”
(DS39947)
for detailed information on Device and Revision IDs for your specific device.
2010-2017 Microchip Technology Inc.
DS80000500N-page 1
PIC18F87K90 FAMILY
TABLE 2:
Module
SILICON ISSUE SUMMARY
Feature
Item
Number
Affected Revisions
(1)
Issue Summary
A3 B1 B3 B5 C1 C3 C5 C6
The 12-bit A/D performance is
outside of the data sheet’s A/D
Converter specifications.
The 12-bit A/D performance is
outside of the data sheet’s A/D
Converter specifications.
I/O port leakage is higher than the
D060 spec in the data sheet.
The high-to-low (VDIRMAG =
0)
setting of the HLVD may send initial
interrupts.
The tri-state setting of the auto-
shutdown feature in the enhanced
PWM will not successfully drive the
pin to tri-state.
When using the Synchronous
Transmit mode, transmitted data
may become corrupted if using the
TXxIF bit to determine when to load
the TXREGx register.
Maximum current limits may be
higher than specified in
Section 31.2 “DC Characteristics:
Power-Down and Supply Current
PIC18F87K90 Family (Industrial)”
of the data sheet.
Entering Ultra Low-Power Sleep
mode, by setting RETEN =
0
and
SRETEN =
1,
will cause the part not
to be programmable through
ICSP™.
Using the WDT to exit Ultra Low-
Power Sleep mode when V
DD
>4.5V
can cause the part to enter a Reset
state requiring POR to exit.
An unexpected Reset may occur if
the Brown-out Reset module (BOR)
is disabled, and then re-enabled,
when the High/Low-Voltage
Detection module (HLVD) is not
enabled (HLVDCON<4> =
0).
RG5 will cause excess pin leakage
whenever it is driven low.
XT Primary Oscillator mode does not
reliably function when the driving
crystals are above 3 MHz.
When the timer is operated in
Asynchronous External Input mode,
unexpected interrupt flag generation
may occur.
X
X
X
X
Analog-to-Digital
Converter (A/D)
Analog-to-Digital
Converter (A/D)
Ports
High/Low-Voltage
Detect (HLVD)
A/D Offset
1.1
A/D Offset
Leakage
HLVD Trip
1.2
2.
3.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ECCP
Auto-Shutdown
4.
X
X
X
X
X
X
X
X
EUSART
Synchronous
Transmit
5.
X
X
X
X
X
X
X
X
I
PD
and I
DD
Maximum
Limit
6.
X
Ultra Low-Power
Sleep
Sleep Entry
7.1
X
X
X
Ultra Low-Power
Sleep
WDT Wake-up
7.2
X
X
X
X
X
X
X
X
Resets (BOR)
Enable/
Disable
8.
X
X
X
X
X
X
X
X
RG5 Pin
Leakage
9.
10.
X
X
X
X
X
Primary Oscillator
XT Mode
Timer1/3/5/7
Interrupt
11.
X
X
X
X
X
X
Note 1:
Only those issues indicated in the columns labeled B5 and C6 apply to the current silicon revision.
DS80000500N-page 2
2010-2017 Microchip Technology Inc.
PIC18F87K90 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B5,
C6).
1.2
The A/D will meet the Microchip standard A/D
specification when used as a 10-bit A/D. When
used as a 12-bit A/D, the possible issues include
high offset error (up to a maximum of ±25 LSBs
at 25°C, ±30 LSBs at 85°C, 125°C and -40°C),
high DNL error (up to a maximum of ±4 LSBs)
and multiple missing codes (up to a maximum of
20). Users should evaluate the 12-bit A/D
performance in their application using the
suggested work around below. See
Table 3
for
guidance specifications.
A/D Offset
The A/D may have high offset error, up to a
maximum of ±25 LSBs at 25°C, ±30 LSBs at 85°C,
125°C and -40°C; it can be used if the A/D is
calibrated for the offset.
Work around
Method to Calibrate for Offset:
In Single-Ended mode, connect A/D +ve input to
ground and take the A/D reading. This will be the
offset of the device and can be used to
compensate for the subsequent A/D readings on
the actual inputs.
1. Module: Analog-to-Digital Converter
(A/D)
1.1
The A/D will meet the Microchip standard A/D
specification when used as a 10-bit A/D. When
used as a 12-bit A/D, the possible issues include
high offset error (up to a maximum of 50 LSBs),
high DNL error (up to a maximum of ±4 LSBs)
and multiple missing codes (up to a maximum
of 20). Users should evaluate the 12-bit A/D
performance in their application using the
suggested work around below.
A/D Offset
The A/D may have high offset error, up to a
maximum of 50 LSB; it can be used if the A/D is
calibrated for the offset.
Work around
Method to Calibrate for Offset:
In Single-Ended mode, connect A/D +ve input to
ground and take the A/D reading. This will be the
offset of the device and can be used to
compensate for the subsequent A/D readings on
the actual inputs.
Affected Silicon Revisions
A1 B1 B3 B5 C1 C3 C5 C6
X
2010-2017 Microchip Technology Inc.
DS80000500N-page 3
PIC18F87K90 FAMILY
TABLE 3:
Param.
No.
A01
A03
A04
A06
Sym.
N
R
E
IL
E
DL
E
OFF
A/D CONVERTER CHARACTERISTICS
Characteristic
Resolution
Integral Linearity Error
Differential Linearity Error
Offset Error
Min.
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
3
—
AV
DD
– AV
SS
V
Max.
12
±10.0
+6.0/-4.0
±25
±30
±15
Units
bit
LSb
LSb
LSb
LSb
LSb
Conditions
V
REF
5.0V
V
REF
5.0V
V
REF
5.0V
V
REF
5.0V,
Temperature: 25°C
V
REF
5.0V,
Temperature:
85°C, -40°C
V
REF
5.0V
V
SS
V
AIN
V
REF
A07
A10
A20
E
GN
—
Gain Error
Monotonicity
(1)
—
V
REF
Reference Voltage
Range
(V
REFH
– V
REFL
)
V
REFH
Reference Voltage High
V
REFL
V
AIN
Reference Voltage Low
Analog Input Voltage
A21
A22
A25
Note 1:
AV
SS
+ 3.0V
AV
SS
– 0.3V
V
REFL
—
—
—
AV
DD
+ 0.3V
AV
DD
– 3.0V
V
REFH
V
V
V
The A/D conversion result never decreases with an increase in the input voltage.
Affected Silicon Revisions
A1
B1
X
B3
X
B5
X
C1
X
C3 C5
X
X
C6
X
DS80000500N-page 4
2010-2017 Microchip Technology Inc.
PIC18F87K90 FAMILY
2. Module: Ports
The input leakage will not match the D060
specification in the data sheet. The leakage will
meet the 200 nA specification at T
A
= 25°C. At
T
A
= 85°C, the leakage will be up to a maximum of
2
A.
Work around
None.
Affected Silicon Revisions
A1
X
B1
B3
X
B5
X
C1
X
C3 C5
X
X
C6
X
5. Module: EUSART
In Synchronous Transmit mode, data may be
corrupted if using the TXxIF bit to determine when
to load the TXREGx register. One or more of the
intended transmit messages may be incorrect.
Work around
A fixed delay added before loading the TXREGx
may not be a reliable work around. When loading
the TXREGx, check that the TRMT bit inside of the
TXSTAx register is set instead of checking the
TXxIF bit. The following code can be used:
EXAMPLE 1:
3. Module: High/Low-Voltage Detect (HLVD)
The high-to-low (VDIRMAG =
0)
setting of the
HLVD may send initial interrupts. High trip points
that are close to the intended operating voltage are
susceptible to this behavior.
Work around
Select a lower trip voltage that allows consistent
start-up or clear any initial interrupts from the
HLVD on start-up.
Affected Silicon Revisions
A1
X
B1
X
B3
X
B5
X
C1
X
C3 C5
X
X
C6
X
EUSART SYNCHRONOUS
TRANSMIT WORK AROUND
while(!TXSTAxbits.TRMT);
// wait to load TXREGx until TRMT is set
Affected Silicon Revisions
A1
X
B1
X
B3
X
B5
X
C1
X
C3 C5
X
X
C6
X
4. Module: ECCP
The tri-state setting of the auto-shutdown feature
in the enhanced PWM will not successfully drive
the pin to tri-state. The pin will remain an output
and should not be driven externally. All tri-state
settings will be affected.
Work around
Use one of the other two auto-shutdown states
available, as outlined in the data sheet.
Affected Silicon Revisions
A1
X
B1
X
B3
X
B5
X
C1
X
C3 C5
X
X
C6
X
2010-2017 Microchip Technology Inc.
DS80000500N-page 5
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