PIC16F526
PIC16F526 Memory Programming Specification
This document includes the
programming specifications for the
following devices:
• PIC16F526
1.1
Hardware Requirements
The PIC16F526 requires one power supply for V
DD
(5.0V) and one for V
PP
(12.5V).
1.2
Program/Verify Mode
1.0
PROGRAMMING THE
PIC16F526
The PIC16F526 is programmed using a serial method.
The Serial mode will allow the PIC16F526 to be pro-
grammed while in the user’s system. This allows for
increased design flexibility. This programming
specification applies to the PIC16F526 devices in all
packages.
The Program/Verify mode for the PIC16F526 allows
programming of user program memory, user ID loca-
tions, backup OSCCAL location and the Configuration
Word.
FIGURE 1-1:
PIC16F526 14-PIN PDIP, SOIC, TSSOP DIAGRAM
V
DD
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
RB3/MCLR/V
PP
RC5/T0CKI
RC4/C2OUT
RC3
1
2
3
4
5
6
7
14
13
V
SS
RB0/C1IN+/AN0/ICSPDAT
RB1/C1IN-/AN1/ICSPCLK
RB2/C1OUT/AN2
RC0/C2IN+
RC1/C2IN-
RC2/CV
REF
PIC16F526
12
11
10
9
8
TABLE 1-1:
Pin Name
RB1
RB0
MCLR/V
PP
/RB3
V
DD
V
SS
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Function
ICSPCLK
ICSPDAT
Program/Verify mode
V
DD
V
SS
Pin Type
I
I/O
P
(1)
P
P
Pin Description
Clock input – Schmitt Trigger input
Data input/output – Schmitt Trigger input
Programming Power
Power Supply
Ground
Legend:
I = Input, O = Output, P = Power
Note 1:
In the PIC16F526, the programming high voltage is internally generated. To activate the Program/Verify
mode, high voltage of I
IHH
current capability (see Table 6-1) needs to be applied to the MCLR input.
©
2007 Microchip Technology Inc.
DS41317B-page 1
PIC16F526
2.0
MEMORY MAPPING
The Program Memory map of the PIC16F526 device is
shown in Figure 2-1. In Program/Verify mode, the
Program Memory extends from 0x000 to 0x7FF.
through 0x443. The Configuration Word is physically
located at 0x7FF, and the backup OSCCAL locations
extend from 0x444 through 0x447.
2.3.1
USER ID LOCATIONS
FIGURE 2-1:
MEMORY MAP
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
Reset Vector
000h
1FFh
200h
3FEh
3FFh
400h
A user may store identification information (ID) in four
user ID locations. The user ID locations are mapped in
[0x440:0x443]. It is recommended that users use only
the four Least Significant bits (LSb) of each user ID
location and program the upper 8 bits as ‘1’s. The user
ID locations read out normally, even after code protec-
tion is enabled. It is recommended that user ID location
is written as ‘1111
1111 bbbb’
where ‘bbbb’ is user
ID information.
User Memory
Space
Data Memory
Space
2.3.2
CONFIGURATION WORD
Flash Data Memory
User ID Locations
Backup OSCCAL
Locations
43Fh
440h
443h
444h
447h
448h
The Configuration Word is physically located at 0x7FF.
It is only available upon Program mode entry. Once an
Increment Address command is issued, the Configura-
tion Word is no longer accessible, regardless of the
address of the program counter.
Note:
By convention, the Configuration Word is
stored at the logical address location of
0xFFF within the hex file generated for the
PIC16F526. This logical address location
may not reflect the actual physical address
for the part itself. It is the responsibility of
the programming software to retrieve the
Configuration Word from the logical
address within the hex file and granulate
the address to the proper physical location
when programming.
Configuration Memory
Space
Reserved
49Fh
4A0h
Unimplemented
7FEh
Configuration Word
7FFh
2.3.3
BACKUP OSCCAL VALUE
2.1
User Memory
The user memory space is the on-chip user program
memory. As shown in Figure 2-1, it extends from 0x000
to 0x3FF and partitions into pages, including Reset
vector at address 0x3FF. Note that the PC will incre-
ment from (0x000-0x3FF) then to 0x400, (not to
0x000).
The backup OSCCAL locations, 0x444-0x447, are the
locations where the OSCCAL values are stored during
testing of the INTOSC. This location is not erased dur-
ing a standard Bulk Erase, but is erased if the PC is
moved into configuration memory prior to invoking a
Bulk Erase. If this value is erased, it is the user’s
responsibility to rewrite it back to this location for future
use.
2.2
Data Memory
2.4
Oscillator Calibration Bits
The data memory space is the Flash data memory
block and is located at addresses PC = 400h-43Fh. All
program mode commands that work on the normal
Flash memory work on the Flash data memory block.
This includes Bulk Erase, Load and Read Data
commands.
2.3
Configuration Memory
The oscillator Calibration bits are stored at the Reset
vector as the operand of a
MOVLW
instruction. Program-
ming interfaces must allow users to program the
Calibration bits themselves for custom trimming of the
INTOSC. Capability for programming the Calibration
bits when programming the entire memory array must
also be maintained for backwards compatibility.
The configuration memory space extends from 0x440
to 0x7FF. Locations from 0x448 through 0x49F are
reserved. The user ID locations extend from 0x440
DS41317B-page 2
©
2007 Microchip Technology Inc.
PIC16F526
3.0
3.1
COMMANDS AND
ALGORITHMS
Program/Verify Mode
3.1.2
SERIAL PROGRAM/VERIFY
OPERATION
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising V
DD
pin from
V
IL
to V
DD
. Then raise V
PP
from V
IL
to V
IHH
. Once in
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at V
IL
). This means
that all I/Os are in the Reset state (high-impedance
inputs).
3.1.1
PROGRAMMING
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x7FF. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1:
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
T
PPDP
T
HLD
0
The RB1 pin is used as a clock input pin, and the RB0
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB1) is cycled 6 times. Each command bit is
latched on the falling edge of the clock with the Least
Significant bit (LSb) of the command being input first.
The data on pin RB0 is required to have a minimum
setup and hold time of 100 ns with respect to the falling
edge of the clock. Commands that have data associ-
ated with them (Read and Load) are specified to have
a minimum delay of 1 µs between the command and
the data. After this delay the clock pin is cycled 16 times
with the first cycle being a Start bit and the last cycle
being a Stop bit. Data is also input and output LSb first,
with data input being latched on the falling edge of the
clock and data output being driven on the rising edge of
the clock. Therefore, during a Read operation the LSb
will be transmitted onto pin RB0 on the rising edge of
the second cycle, and during a Load operation the LSb
will be latched on the falling edge of the second cycle.
A minimum 1 µs delay is also specified between con-
secutive commands; except the “End Programming”
command which requires a 100 µs delay. Because this
is a 12-bit core, the two MSbs of the data word are
ignored. The commands that are available are
described in Table 3-1.
V
PP
V
DD
RB0
(ICSPDAT)
RB1
(ICSPCLK)
TABLE 3-1:
COMMAND MAPPING LOAD DATA
Command
Mapping
(MSb ... LSb)
X X 0 0 1 0
X X 0 1 0 0
X X 0 1 1 0
X X 1 0 0 0
X X 1 1 1 0
X X 1 0 0 1
Hex
Value
2
4
6
8
E
9
Data
start_bit, data (14), stop_bit
start_bit, data (14), stop_bit
Load Data
Read Data
Increment Address
Begin Programming
End Programming
Bulk Erase Program Memory
©
2007 Microchip Technology Inc.
DS41317B-page 3
PIC16F526
3.1.2.1
Load Data
After receiving this command, the device will clock in
14 bits as a “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-2.
FIGURE 3-2:
RB1
(ICSPCLK)
RB0
(ICSPDAT)
LOAD DATA COMMAND (PROGRAM/VERIFY)
1
2
3
4
5
6
T
DLY
2
1
2
3
4
5
15
16
0
1
0
T
SET
1
T
HLD
1
0
x
x
strt_bit
LSb
T
SET
1
-+
T
HLD
1
MSb
stp_bit
T
DLY
1
3.1.2.2
Read Data
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The RB0
pin will go into Output mode on the second rising clock
edge and it will revert back to Input mode (high-imped-
ance) after the 16th rising edge. Because this is a 12-bit
core, the two MSbs will read as ‘1’. A timing diagram of
this command is shown in Figure 3-3.
FIGURE 3-3:
READ DATA FROM PROGRAM MEMORY COMMAND
T
DLY
2
RB1
(ICSPCLK)
RB0
(ICSPDAT)
1
1
2
3
4
5
6
1
2
3
T
DLY
3
4
5
15
16
0
0
T
SET
1
1
0
x
x
strt_bit
T
DLY
1
MSb
stp_bit
LSb
T
HLD
1
Input
Output
Input
DS41317B-page 4
©
2007 Microchip Technology Inc.
PIC16F526
3.1.2.3
Increment Address
The PC is incremented when this command is
received.
FIGURE 3-4:
V
IHH
MCLR/V
PP
INCREMENT ADDRESS COMMAND (SERIAL PROGRAM/VERIFY)
T
DLY
2
1
2
3
4
5
6
1 µs min.
Next Command
1
2
RB1
(ICSPCLK)
RB0
(ICSPDAT)
0
1
1
T
SET
1
}
100 ns
min.
Reset
}
0
X
T
HLD
1
X
3.1.2.4
Begin Programming
A Load command (Load Data) must be given before
every Begin Programming command. Programming of
the appropriate memory (User Program Memory, Flash
Data Memory or Test Program Memory) will begin after
this command is received and decoded.
FIGURE 3-5:
V
IHH
MCLR/V
PP
BEGIN PROGRAMMING COMMAND
T
PROG
1
2
3
4
5
6
Next Command
1
2
RB1
(ICSPCLK)
RB0
(ICSPDAT)
0
1
X
0
0
T
SET
1
}
X
T
HLD
1
100 ns
min.
Reset
}
©
2007 Microchip Technology Inc.
DS41317B-page 5
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