PIC18F47J53 FAMILY
PIC18F47J53 Family
Silicon Errata and Data Sheet Clarification
The PIC18F47J53 Family devices that you have
received conform functionally to the current Device
Data Sheet (DS39964B), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be
addressed in future revisions of the PIC18F47J53
Family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2
apply to the current silicon
revision (A1).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device,
and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select
Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number
and
Device
Revision ID value appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
2.
3.
4.
Data Sheet clarifications and corrections start on page 6,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s pro-
grammers, debuggers, and emulation tools, which are
available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC18F47J53
Family silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Part Number
PIC18F47J53
PIC18F46J53
PIC18F27J53
PIC18F26J53
PIC18LF47J53
PIC18LF46J53
PIC18LF27J53
PIC18LF26J53
Device ID
(1)
2C7h
2C5h
2C3h
2C1h
2D7h
2D5h
2D3h
2D1h
01h
Revision ID for Silicon Revision
(2)
A1
Note 1:
2:
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the
“PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification”
(DS39687)
for detailed information on Device and Revision IDs for your specific device.
2010 Microchip Technology Inc.
DS80506C-page 1
PIC18F47J53 FAMILY
TABLE 2:
Module
SILICON ISSUE SUMMARY
Feature
Constant
Current
Source
Item
Number
Issue Summary
Band gap must be manually enabled before using the
CTMU.
PLL can not be enabled unless the 8 or 4 MHz INTOSC
option is set.
ANx pin may output a pull-up pulse during acquisition.
Receive and transmit baud rates differ due to different clock
sources.
If a Stop condition occurs in the middle of an address or
data reception, there will be issues with the SCL clock
stream and RCEN bit.
In I
2
C slave reception, the module may have problems
receiving correct data.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 T
CY
delay.
Affected
Revisions
(1)
A1
CTMU
1.
2.
3.
4.
5.
6.
7.
X
X
X
X
X
X
X
Oscillator
PLL
Configurations
ADC
EUSART
MSSP
MSSP
EUSART
Note 1:
A/D
Receive
Baud Rate
I
2
C™
Mode
I
2
C Slave
Reception
Enable/
Disable
Only those issues indicated in the last column apply to the current silicon revision.
DS80506C-page 2
2010 Microchip Technology Inc.
PIC18F47J53 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
3. Module: Analog-to-Digital Converter
(ADC)
At the beginning of sample acquisition, one or
more small pull-up pulses (approximately 25 ns
long) may output to the currently selected ANx
analog channel. These pulses can lead to a pos-
itive offset error when the analog signal voltage
is near V
SS
and the external analog signal driver
is unable to dissipate the added pull-up voltage
before the A/D conversion occurs.
Work around
Do one or more of the following:
• Use the “0 T
AD
” A/D acquisition time setting to
start the next sample acquisition period imme-
diately following an A/D conversion
completion.
This allows the external analog signal driver
more time to dissipate the pull-up pulses that
occur when the sample acquisition is started.
• Use a longer A/D acquisition time setting to
provide time for the external analog signal
driver to dissipate the pull-up pulse voltage.
• Use low-impedance, active analog signal
drivers to reduce the time needed to dissipate
the pull-up pulse voltage.
• Experiment with external filter capacitor val-
ues to avoid allowing the pull-up voltage offset
to affect the final voltage that gets converted.
Small filter capacitor values (or none at all) will
allow time for the external analog signal driver to
dissipate the pull-up voltage quickly. Alternately,
large filter capacitor values will prevent the short
pull-up pulses from increasing the final voltage
enough to cause an A/D conversion error.
Affected Silicon Revisions
A1
X
1. Module: Charge Time Measurement Unit
(CTMU)
When using the CTMU, the constant current
source may not output if the internal band gap
reference is not enabled.
Work around
Before using the CTMU, the internal band gap ref-
erence module should be manually enabled by
setting the VBGEN bit to ‘1’ (ANCON1<7> =
1).
Affected Silicon Revisions
A1
X
2. Module: Phase Locked Loop (PLL)
When OSCCON<6:4> are configured to settings
other than a 4 MHz or 8 MHz INTOSC post-
scaler, the PLLEN bit (OSCTUNE<6>) is forced
to ‘0’, even if firmware tries to set the PLLEN bit.
This may prevent firmware from enabling the
PLL.
Work around
Before attempting to set the PLLEN bit, config-
ure OSCCON<6:4> to ‘0b110’ or ‘0b111’ to
select the 4 MHz or 8 MHz INTOSC postscaler.
Affected Silicon Revisions
A1
X
2010 Microchip Technology Inc.
DS80506C-page 3
PIC18F47J53 FAMILY
4. Module: EUSART (Receive Baud Rate)
The EUSART may transmit and receive at
different baud rates under the following
circumstances:
• a system clock source other than the
Secondary Oscillator has been selected, and
• a CPU clock divider (CPDIV<1:0>,
CONFIG1H<1:0>) other than 1:1 has been
programmed.
This is because the receive baud rate clock
source is generated from a point prior to the
CPU prescaler, while the rest of the logic is
clocked at the system clock frequency (following
the prescaler).
Work around
Several work arounds are presented; others
may be available.
• If possible, use only a CPU divider of 1:1
(CPDIV<1:0> =
11).
• If the EUSART is being used to receive data
only, calculate the baud rate on the predivided
clock frequency. For example, if the system
clock frequency is 8 MHz and a CPU divider
setting of 2 is being used, use a clock
frequency of 16 MHz to calculate baud rate.
• Use two USART modules for communication:
one to transmit data, and one to receive.
Calculate the baud rate for the receive
USART as described in the previous work
around. Calculate the transmit baud rate
normally using the actual (post-divider) clock
speed.
Affected Silicon Revisions
A1
X
5. Module: Master Synchronous Serial Port
In Master I
2
C Receive mode, if a Stop condition
occurs in the middle of an address or data
reception, the SCL clock stream will continue
endlessly and the RCEN bit of the SSPxCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condi-
tion, nine additional clocks will be generated
followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop con-
dition, and subsequently, the stuck RCEN bit.
Clear the stuck RCEN bit by clearing the SSPEN
bit of SSPxCON1.
Affected Silicon Revisions
A1
X
6. Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C™ slave reception, the
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer register (SSPxBUF) is
not read after the SSP1IF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature. This is done by setting
the SEN bit (SSPxCON2<0>).
• Each time the SSPxIF is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
A1
X
DS80506C-page 4
2010 Microchip Technology Inc.
PIC18F47J53 FAMILY
7. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
(RCSTAx<7>) =
0)
• The EUSART is re-enabled (RCSTAx<7> =
1)
• A two-cycle instruction is executed immediately
after setting SPEN, CREN or TXEN =
1
Work around
Add a 2 T
CY
delay after any instruction that re-
enables the EUSART module (sets SPEN, CREN
or TXEN =
1).
See
Example 1.
Affected Silicon Revisions
A1
X
EXAMPLE 1:
RE-ENABLING AN EUSART MODULE
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
RCSTA1, SPEN
;or RCSTA2 if EUSART2
nop
;1 Tcy delay
nop
;1 Tcy delay (two total)
2010 Microchip Technology Inc.
DS80506C-page 5
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