TMP86FM29
Comparison table of TMP86C829B/H29B/M29B/PM29A/PM29B/C929AXB and TMP86FM29
TMP86C829B
TMP86CH29B
TMP86CM29B
ROM
8 K (Mask ROM)
16 K (Mask ROM)
32 K (Mask ROM)
512
1.5 K
1.5 K
42 pin
5 pin
10-bit AD converter
×
8 ch
18-bit timer
×
1 ch
8-bit timer
×
4 ch
8-bit UART / SIO
×
1 ch
32 seg
×
4 com
4 ch
1.8 to 5.5 V at 4.2 MHz
2.7 to 5.5 V at 8 MHz
4.5 to 5.5 V at 16 MHz
−40
to 85℃
−
N/A
1.8 to 5.25 V at 4.2 MHz
2.7 to 5.25 V at 8 MHz
4.5 to 5.25 V at 16 MHz
0 to 60°C
TMP86PM29A
TMP86PM29B
TMP86C929AXB
(Emulation chip)
(Note 3)
−
TMP86FM29F
Difference
32 K (OTP)
32 K (Flash)
RAM
I/O
External
Interrupt
AD Converter
Timer Counter
Serial Interface
LCD
Key-on
Wakeup
Operating
Voltage
in MCU Mode
Operating
Temperature
in MCU Mode
Writing to
Flash Memory
CPU Wait (Note 1)
1.5 K
−
42 pin (MCU part)
2K
42 pin
5 pin
10-bit AD converter
×
8 ch
18-bit timer
×
1 ch
8-bit timer
×
4 ch
8-bit UART / SIO
×
1 ch
32 seg
×
4 com (Note 2)
4 ch
1.8 to 3.6 V at 4.2 MHz (External clock)
1.8 to 3.6 V at 8 MHz (Resonator)
2.7 to 3.6 V at 16 MHz
−40
to 85°C
2.7 to 3.6V at 16 MHz
25°C
±
5°C
Available
Note 1: The CPU wait is a CPU halt function for stabilizing of power supply of Flash memory. The CPU wait
period is as follows. In the CPU wait period except RESET, CPU is halted but peripheral functions
are not halted. Therefore, if the interrupt occurs during the CPU wait period, the interrupt latch is set.
In this case, if the IMF has been set to “1”, the interrupt service routine is executed after CPU wait
period. For details refer to 2.14 “Flash Memory” in TMP86FM29 data sheet.
Thus, even if the same software is executed in 86FM29 and 86C829B/H29B/M29B/PM29A/PM29B
/C929AXB, the operation process is not the same. Therefore, when the final operating confirmation
on target application is executed for software development of Mask ROM Product
(86C829B/H29B/M29B), not the Flash product (86FM29) but the OTP product (86PM29A/PM29B)
should be used.
Condition
After reset release
Changing from STOP mode to NORMAL mode
(at EEPCR<MNPWDW>
=
“1”)
Changing from STOP mode to SLOW mode
(at EEPCR<MNPWDW>
=
“1”)
Changing from IDLE0/1/2 mode to NORMAL mode
(at EEPCR<ATPWDW>
=
“0”)
Changing from SLEEP0/1/2 mode to SLOW mode
(at EEPCR<ATPWDW>
=
“0”)
Wait Time
2 /fc[s]
2 /fc[s]
2 /fs[s]
2 /fc[s]
2 /fs[s]
3
10
3
10
10
Halt/Operate
CPU
Halt
Halt
Halt
Halt
Halt
Peripherals
Halt
Operate
Operate
Operate
Operate
2004-03-01
TMP86FM29
Note 2: The 86FM29 can not drive the 5V LCD panel because the electrical characteristics in 86FM29 is
altered from 86C829B/H29B/M29B/PM29A/PM29B/C929AXB. The recommended operating
condition of V3 pin in TMP86FM29 is 3.6V(max). For details, refer to “Electrical Characteristics”.
When the LCD booster circuit is used in 86FM29, connect the reference voltage and capacitor as
shown in "case2". Though the method of "case1" has been recommended in 86C829B
/H29B/M29B/PM29A/PM29B datasheets, the 86FM29 should not use method of "case1". Even if the
method of "case1" is used in the 86C829B/H29B/M29B/PM29A/PM29B/C929AXB, the function and
operation are not issue at all. However, if the "case2" is used, the booster ability becomes higher
than "case1". Therefore, when the application board is designed newly in future, the method of
"case2" is also recommended in 86C829B/H29B/M29B/PM29A/PM29B/C929AXB.
VDD
V3
V2
C0
C
C1
VSS
V1
Reference voltage
(1 V)
VSS
Case 2
(For 86FM29 and 86C829B/H29B/M29B/
PM29A/PM29B/C929AXB)
C
C
VDD
V3
V2
V1
C
C
Reference voltage
(1 V)
C
C1
C0
Case 1
(For 86C829B/H29B/M29B/PM29A/PM29B/C929AXB)
Note 3: Flash function, CPU wait period and serial PROM mode cannot be emulated in the 86C929AXB. If
the software including the flash function is executed in 86C929AXB, the operation process differs
from 86FM29.
2004-03-01
TMP86FM29
CMOS 8-Bit Microcontroller
TMP86FM29UG/FG
The TMP86FM29 is the high-speed, high-performance and low power consumption 8-bit
microcomputer, including FLASH, RAM, LCD driver, multi-function timer/counter, serial interface
(UART/SIO), a 10-bit AD converter and two clock generators on chip.
Product No.
TMP86FM29UG
TMP86FM29FG
FLASH
32768
×
8 bits
RAM
1536
×
8 bits
Package
P-LQFP64-1010-0.50E
P-QFP64-1414-0.80C
Emulation Chip
TMP86C929AXB
Feautures
♦
♦
♦
♦
♦
♦
•
8-bit single chip microcomputer TLCS-870/C series
Instruction execution time: 0.25
µs
(at 16 MHz)
122
µs
(at 32.768 kHz)
132 types and 731 basic instructions
19 interrupt sources (External: 5, Internal: 14)
Input/Output ports (39 pins)
(Out of which 24 pins are also used as SEG pins)
18-bit timer counter: 1 ch
Timer, Event counter,
Pulse width measurement,
Frequencymeasurement modes
8-bit timer counter: 4 ch
•
Timer, Event counter,
PWM output, Programmable divider output,
PPG output modes
Time Base Timer
Divider output function
030619EBP1
P-LQFP64-1010-0.50E
TMP86FM29UG
P-QFP64-1414-0.80C
♦
TMP86FM29FG
♦
♦
•
The information contained herein is subject to change without notice.
•
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
•
The products described in this document are subject to the foreign exchange and foreign trade laws.
•
TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any
law and regulations.
•
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
86FM29-1
2004-03-01
TMP86FM29
♦
♦
♦
•
♦
♦
•
•
•
•
♦
•
♦
•
•
•
•
•
•
•
•
♦
Watchdog Timer
•
Interrupt source/reset output (programmable)
Serial interface
•
8-bit UART/SIO: 1ch
10-bit successive approximation type AD converter
Analog input: 8 ch
Four Key-On Wake-Up pins
LCD driver/controller
Built-in voltage booster for LCD driver
With displaymemory
LCD direct drive capability (max 32 seg
×
4 com)
1/4, 1/3, 1/2duties or static drive are programmably selectable
Dual clock operation
Single/Dual-clock mode
Nine power saving operating modes
STOP mode
: Oscillation stops. Battery/Capacitor back-up.
Port output hold/High-impedance.
SLOW 1, 2 mode : Low power consumption operation using low-frequency clock (32.768 kHz)
IDLE 0 mode
: CPU stops, and peripherals operate using high-frequency clock of
Time-Base-Timer. Release by falling edge of TBTCR
<TBTCK>
setting.
IDLE 1 mode
: CPU stops, and peripherals operate using high-frequency clock.
Release by interruputs.
IDLE 2 mode
: CPU stops, and peripherals operate using high and low frequency clock.
Release by interruputs.
SLEEP 0 mode : CPU stops, and peripherals operate using low-frequency clock of
Time-Base-Timer. Release by falling edge of TBTCR
<TBTCK>
setting.
SLEEP 1 mode : CPU stops, and peripherals operate using low-frequency clock.
Release by interrupts.
SLEEP 2 mode : CPU stops, and peripherals operate using high and low frequency clock.
Release by interrupts.
1.8 to 3.6 V at 8 MHz/32.768 kHz
2.7 to 3.6 V at 16 MHz/32.768 kHz
Wide operating voltage:
86FM29-2
2004-03-01
TMP86FM29
Pin Assignments
(Top View)
P-LQFP64-1010-0.50E
P-QFP64-1414-0.80C
SEG3
SEG4
SEG5
SEG6
SEG7
P77 (SEG8)
P76 (SEG9)
P75 (SEG10)
P74 (SEG11)
P73 (SEG12)
P72 (SEG13)
P71 (SEG14)
P70 (SEG15)
P57 (SEG16)
P56 (SEG17)
P55 (SEG18)
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
V3
V2
V1
C1
C0
(
DVO
) P30
(
PWM3
/
PDO3
/TC3) P31
(
PWM4
/
PDO4
/
PPG4
/TC4) P32
(
PWM6
/
PDO6
/
PPG6
/TC6) P33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
XIN
XOUT
TEST
VDD
(XTIN) P21
(XTOUT) P22
RESET
(
STOP
/
INT5
)
(AIN0)
(AIN1/ECIN)
(AIN2/ECNT)
(AIN3/INT0)
(AIN4/STOP2)
(AIN5/STOP3)
(AIN6/STOP4)
P20
P60
P61
P62
P63
P64
P65
P66
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P54 (SEG19)
P53 (SEG20)
P52 (SEG21)
P51 (SEG22)
P50 (SEG23)
P17 (SEG24/
SCK
)
P16 (SEG25/TXD/SO)
P15 (SEG26/RXD/SI/BOOT)
P14 (SEG27/INT3)
P13 (SEG28/INT2)
P12 (SEG29/INT1)
P11 (SEG30)
P10 (SEG31)
AVDD
VAREF
P67 (AIN7/STOP5)
86FM29-3
2004-03-01
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