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AS7C33256PFS18B-200TQI

Description
3.3V 256K X 18 pipeline burst synchronous SRAM
Categorystorage    storage   
File Size525KB,19 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C33256PFS18B-200TQI Overview

3.3V 256K X 18 pipeline burst synchronous SRAM

AS7C33256PFS18B-200TQI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP, QFP100,.63X.87
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time6.5 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density4718592 bi
Memory IC TypeSTANDARD SRAM
memory width18
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.03 A
Minimum standby current3.14 V
Maximum slew rate0.4 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
December 2004
®
AS7C33256PFS18B
3.3V 256K
×
18 pipeline burst synchronous SRAM
Features
Organization: 262,144 words × 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.0/3.5/4.0 ns
Fast OE access time: 3.0/3.5/4.0 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[17:0]
CLK
CS
CLR
Burst logic
18
16
18
18
18
Q
D
Address
CS
register
CLK
256K × 18
Memory
array
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
CLK
D
Byte Write
registers
Byte Write
registers
Enable
register
Q
OE
2
Input
registers
CLK
CE
CLK
ZZ
Output
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ [a,b]
Selection guide
–200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
130
30
–166
6
166
3.5
350
100
30
–133
7.5
133
4
325
90
30
Units
ns
MHz
ns
mA
mA
mA
12/10/04; v.1.7
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
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