ADS8402
SLAS154B – DECEMBER 2002 – REVISED MAY 2003
16-BIT, 1.25 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICRO POWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
FEATURES
D
1.25-MHz Sample Rate
D
16-Bit NMC Ensured Over Temperature
D
Zero Latency
D
Unipolar Differential Input Range: V
ref
to –V
ref
D
Onboard Reference
D
Onboard Reference Buffer
D
High-Speed Parallel Interface
D
Power Dissipation: 155 mW at 1.25 MHz Typ
D
Wide Digital Supply
D
8-/16-Bit Bus Transfer
D
48-Pin TQFP Package
APPLICATIONS
D
DWDM
D
Instrumentation
D
High-Speed, High-Resolution, Zero Latency
D
D
D
Data Acquisition Systems
Transducer Interface
Medical Instruments
Communication
DESCRIPTION
The ADS8402 is a 16-bit, 1.25 MHz A/D converter with an
internal 4.096-V reference. The device includes a 16-bit
capacitor-based SAR A/D converter with inherent sample
and hold. The ADS8402 offers a full 16-bit interface and an
8-bit option where data is read using two 8-bit read cycles.
The ADS8402 has a unipolar differential input. It is
available in a 48-lead TQFP package and is characterized
over the industrial –40°C to 85°C temperature range.
SAR
+IN
–IN
REFIN
+
_
Output
Latches
and
3-State
Drivers
BYTE
16-/8-Bit
Parallel DATA
Output Bus
CDAC
Comparator
RESET
Conversion
and
Control Logic
CONVST
BUSY
CS
RD
REFOUT
4.096-V
Internal
Reference
Clock
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
2002–2003, Texas Instruments Incorporated
ADS8402
www.ti.com
SLAS154B – DECEMBER 2002 – REVISED MAY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO
MISSING
CODES
RESOLU-
TION (BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPER-
ATURE
RANGE
ORDERING
INFORMATION
TRANS-
PORT
MEDIA
QUANTITY
Tape and
reel 250
Tape and
reel 1000
Tape and
reel 250
Tape and
reel 1000
MODEL
ADS8402IPFBT
ADS8402I
±6
–2~+3
2 3
15
48 Pin
TQFP
PFB
–40 C
–40°C to
85°C
ADS8402IPFBR
ADS8402IBPFBT
ADS8402IB
±3.5
±3
5
–1~+2
1 2
16
48 Pin
TQFP
PFB
–40 C
–40°C to
85°C
ADS8402IBPFBR
NOTE: For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
+IN to AGND
Voltage
–IN to AGND
+VA to AGND
Voltage range
+VBD to BDGND
+VA to +VBD
Digital input voltage to BDGND
Digital output voltage to BDGND
Operating free-air temperature range, TA
Storage temperature range, Tstg
Junction temperature (TJ max)
Power dissipation
TQFP package
θ
JA thermal impedance
Vapor phase (60 sec)
Lead temperature soldering
temperature,
Infrared (15 sec)
+VA + 0.1 V
+VA + 0.1 V
–0.3 V to 7 V
–0.3 V to 7 V
–0.3 V to 2.5 V
–0.3 V to +VBD + 0.3 V
–0.3 V to +VBD + 0.3 V
–40°C to 85°C
–65°C to 150°C
150°C
(TJMax – TA)/θJA
86°C/W
215°C
220°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ADS8402
www.ti.com
SLAS154B – DECEMBER 2002 – REVISED MAY 2003
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted)
PARAMETER
Analog Input
Full-scale input voltage (see Note 1)
Absolute input voltage
Common-mode input range
Input capacitance
Input leakage current
System Performance
Resolution
ADS8402I
No missing codes
Integral linearity (see Notes 2 and 3)
Differential linearity
Differentiallinearity
Offset error (see Note 4)
Gain error (see Notes 4 and 5)
Common-mode
Common mode rejection ratio
Noise
DC Power supply rejection ratio
Sampling Dynamics
Conversion time
Acquisition time
Throughput rate
Aperture delay
Aperture jitter
Step response
Overvoltage recovery
(1) Ideal input span, does not include gain or offset error.
(2) LSB means least significant bit
(3) This is endpoint INL, not best fit
(4) Measured relative to an ideal full-scale input (+IN – –IN) of 8.192 V
(5) This specification does not include the internal reference voltage error and drift.
2
25
100
100
150
1.25
610
ns
ns
MHz
ns
ps
ns
ns
At 7FFFh output code,
+VA = 4.75 V to 5.25 V,
Vref = 4.096 V, See Note 4
ADS8402IB
ADS8402I
ADS8402IB
ADS8402I
ADS8402IB
ADS8402I
ADS8402IB
ADS8402I
ADS8402IB
At dc (±0.2 V around Vref/2)
+IN – –IN = 1 Vpp at 1 MHz
15
16
–6
–3.5
–2
–1
–3
–1.5
–0.15
–0.098
80
80
60
1
dB
µV
RMS
LSB
±2.5
±2
±1
±0.75
±1
±0.5
6
3.5
3
2
3
1.5
0.15
0.098
%FS
LSB
mV
mV
LSB
Bits
16
Bits
ADS8402I
+IN – –IN
+IN
–IN
–Vref
–0.2
–0.2
(Vref
/2)
– 0.2
Vref/2
25
0.5
Vref
Vref + 0.2
Vref + 0.2
(Vref
/2)
+ 0.2
V
V
V
pF
nA
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3
ADS8402
www.ti.com
SLAS154B – DECEMBER 2002 – REVISED MAY 2003
SPECIFICATIONS (CONTINUED)
TA = –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Dynamic Characteristics
Total harmonic distortion (THD) (see Note 1)
Signal-to-noise ratio (SNR)
Signal-to-noise + distortion (SINAD)
Spurious free dynamic range (SFDR)
–3dB Small signal bandwidth
External Voltage Reference Input
Reference voltage at REFIN, Vref
Reference resistance (see Note 2)
Internal Reference Output
Internal reference start-up time
Vref range
Source Current
Line Regulation
Drift
Digital Input/Output
Logic family
VIH
VIL
VOH
VOL
IIH = 5
µA
IIL = 5
µA
IOH = 2 TTL loads
IOL = 2 TTL loads
+VBD–1
–0.3
+VBD – 0.6
0
2’s
Complement
CMO
S
+VBD + 0.3
0.8
+VBD
0.4
V
From 95% (+VA), with 1
µF
storage capacity
IOUT = 0
Static load
+VA = 4.75 ~ 5.25 V
IOUT = 0
0.6
36
4.065
4.096
120
4.13
10
ms
V
µA
mV
PPM/C
2.5
4.096
500
4.2
V
kΩ
VIN = 8 Vpp at 100 kHz
VIN = 8 Vpp at 100 kHz
VIN = 8 Vpp at 100 kHz
VIN = 8 Vpp at 100 kHz
–95
90
88
95
5
dB
dB
dB
dB
MHz
MAX
UNIT
Logic level
L i l
l
Data format
Power Supply Requirements
+VBD (see Notes 3 and 4)
Power supply voltage
P
l
lt
+VA (see Note 4)
fs = 1.25 MHz
fs = 1.25 MHz
+VA Supply current (see Note 5)
Power dissipation (see Note 5)
Temperature Range
2.95
4.75
3.3
5
31
155
5.25
5.25
34
V
V
mA
mW
°C
Operating free-air
–40
85
(1) Calculated on the first nine harmonics of the input frequency
(2) Can vary
±20%
(3) The difference between +VA and +VBD should not be less than 2.3 V, i.e., if +VA is 5.25 V, +VBD should be minimum of 2.95 V.
(4) +VBD
≥
+VA – 2.3 V
(5) This includes only VA+ current. +VBD current is typically 1 mA with 5 pF load capacitance on output pins.
4
ADS8402
www.ti.com
SLAS154B – DECEMBER 2002 – REVISED MAY 2003
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)
PARAMETER
tCONV
tACQ
tpd1
tpd2
tw1
tsu1
tw2
tw3
tw4
th1
td1
tsu2
tw5
ten
td2
td3
tw6
th2
tpd4
tsu3
th3
tdis
Conversion time
Acquisition time
CONVST low to conversion started (BUSY high)
Propagation delay time, End of conversion to BUSY low
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE input
changes) after CONVST low
Delay time, CS low to RD low
Setup time, RD high to CS high
Pulse duration, RD low time
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BYTE rising edge
or falling edge to data valid
RD high
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge
Setup time, BYTE rising edge to RD falling edge
Hold time, BYTE falling edge to RD falling edge
Disable time, RD High (CS high for read cycle) to 3-stated data bus
0
2
20
50
Max(td5)
0
0
20
0
20
40
0
0
50
20
Min(tACQ)
630
20
0
20
10
150
35
20
MIN
TYP
600
MAX
610
UNIT
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td5
Delay time, BUSY low to MSB data valid
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
5
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