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TMC2490A
Multistandard Digital Video Encoder
Features
• All-digital video encoding
• Internal digital subcarrier synthesizer
• 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE
125M input format
• CCIR-624/SMPTE-170M compliant output
• Switchable chrominance bandwidth
• Switchable pedestal with gain compensation
• Pre-programmed horizontal and vertical timing
• 13.5 Mpps pixel rate
• Master or slave (CCIR656) operation
• MPEG interface
• Internal interpolation filters simplify output
reconstruction filters
• 10-bit D/A converters for video reconstruction
• Supports NTSC and PAL standards
• Closed-caption waveform insertion
• Simultaneous S-Video (Y/C) output
• Controlled edge rates
• Single +5V power supply
• 44 lead PLCC package
• Parallel and serial control interface
Applications
• Set-top digital cable television receivers
• Set-top digital satellite television receivers
• Studio parallel CCIR-601 to analog conversion
Description
The TMC2490A video encoder converts digital component
video (in 8-bit parallel CCIR-601/656 or ANSI/SMPTE
125M format) into a standard analog baseband television
(NTSC, NTSC-EIA, and all PAL standards) signal with a
modulated color subcarrier. Both composite (single lead) and
S-Video (separate chroma and luma) formats are active
simultaneously at all three analog outputs. Each video output
generates a standard video signal capable of driving a singly-
or doubly-terminated 75 Ohm load.
The TMC2490A is intended for all non-Macrovision
encoder applications.
The TMC2490A is fabricated in a submicron CMOS
process and is packaged in a 44-lead PLCC. Performance is
guaranteed over the full 0
°
C to 70
°
C operating temperature
range.
Block Diagram
LPF
B-Y
PD
7-0
PIXEL DATA
DEMUX AND
SYNC
EXTRACT
PXCK
Y
HSYNC
VSYNC, B/T
SELC
PDC/CBSEL
DIGITAL
SYNC AND
BLANK
GENERATOR
INTER-
POLATION
FILTER
REF
SERIAL/PARALLEL CONTROL
GLOBAL
CONTROL
V
REF
C
BYP
R
REF
65-2490(1)A-01
INTERPOLATOR
4:2:2 TO 4:4:4
R-Y
LPF
CHROMA
MODULATOR
INTER-
POLATION
FILTER
10-BIT
D/A
CHROMA
S-VIDEO
LUMA
COMPOSITE
SUBCARRIER
SYNTHESIZER
10-BIT
D/A
10-BIT
D/A
SERIAL
PARALLEL
SA
1
SA
0
ADR
SDA
R/W
SCL
CS
D
7-0
D
7-0
SER
RESET
REV. 1.0.2 2/27/02
TMC2490A
PRODUCT SPECIFICATION
Functional Description
The TMC2490A is a fully-integrated digital video encoder
with simultaneous composite and Y/C (S-Video) outputs,
compatible with NTSC, NTSC-EIA, and all PAL television
standards.
Digital component video is accepted at the PD port in 8-bit
parallel CCIR-601/656 format. It is demultiplexed into
luminance and chrominance components. The chrominance
components modulate a digitally synthesized subcarrier.
The luminance and chrominance signals are then separately
interpolated to twice the input pixel rate and converted to
analog signals by 10-bit D/A converters. They are also
digitally combined and the resulting composite signal is
output by a third 10-bit D/A converter.
The TMC2490A operates from a single clock at 27 MHz,
twice the system pixel rate. Programmable control registers
allow software control of subcarrier frequency and phase
parameters. Incoming YC
B
C
R
422 digital video is interpo-
lated to YC
B
C
R
444 format for encoding.
Internal control registers can be accessed over a standard
8-bit parallel microprocessor port or a 2-pin (clock and data)
serial port.
Chroma Modulator
A digital subcarrier synthesizer generates the reference for
a quadrature modulator, producing a digital chrominance
signal. The chroma bandwidth may be programmed to
650 kHz or 1.3 MHz.
Interpolation Filters
Interpolation filters on the luminance and chrominance
signals double the pixel rate to 27Mpps before D/A conver-
sion. This low-pass filtering and oversampling process
reduces sin(x)/x roll-off, and greatly simplifies the analog
reconstruction filter required after the D/A converters.
D/A Converters
Analog outputs of the TMC2490A are driven by three 10-bit
D/A converters, The outputs drive standard video levels into
37.5 or 75 Ohm loads. An internal voltage reference is used
to provide reference current for the D/A converters. An
external fixed or variable voltage reference source can also
be used. The video signal levels from the TMC2490A may
be adjusted to overcome the insertion loss of analog low-pass
output filters by varying R
REF
or V
REF
.
Parallel and Serial Microprocessor Interfaces
The parallel microprocessor interface employs 11 pins.
These are shared with the serial interface. A single pin, SER,
selects between the two interface modes.
In parallel interface mode, one address pin is decoded to
enable access to the internal control register and its pointer.
Controls are reached by loading a desired address through
the 8-bit D
7-0
port, followed by the desired data (read or
write) for that address. The control register address pointer
auto-increments to address 22h and then remains there.
A 2-line serial interface is also provided on the TMC2490A
for initialization and control. The same set of registers
accessed by the parallel port is available to the serial port.
The RESET pin sets all internal state machines and control
registers to their initialized conditions, disables the analog
outputs, and places the encoder in a reset mode. At the rising
edge of RESET, the encoder is automatically initialized in
NTSC-M format.
Sync Generator
The TMC2490A operates in master or slave mode. In slave
mode, it extracts its horizontal and vertical sync timing and
field information from the CCIR-656 SAV (Start of Active
Video) and EAV (End of Active Video) signal in the incom-
ing data stream. In master mode, it generates a 13.5 MHz
timebase and sends line and field synchronizing signals to
the host system.
Horizontal and vertical synchronization pulses in the analog
output are digitally generated by the TMC2490A with con-
trolled rise and fall times on all sync edges, the beginning
and end of active video, and the burst envelope.
MSB
PD
7
PD
7
PD
7
PD
7
C
B
(n)
Y (n)
C
R
(n)
Y (n+1)
Figure 1. Pixel Data Format
LSB
PD
0
PD
0
PD
0
PD
0
2
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
Pin Assignments
SDA/R/W
SA
0
/ADR
SA
1
PD
0
GND
V
DD
PD
1
PD
2
PD
3
PD
4
PD
5
44
6
5
4
3
2
1
43
42
41
18
19
20
21
22
23
24
25
26
27
HSYNC
VSYNC,T/B
CBSEL,PDC
SELC
RESET
V
DD
GND
PXCK
V
DD
V
REF
R
REF
28
SCL/CS
SER
D
7
D
6
D
5
D
4
GND
D
3
D
2
D
1
D
0
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TMC2490A
PD
6
PD
7
V
DD
GND
CHROMA
V
DDA
C
BYP
LUMA
GND
COMPOSITE
GND
65-2490(1)A-02
Pin Descriptions
Pin Name
Clock
PXCK
25
TTL
Pixel Clock Input.
This 27.0 MHz clock is internally divided by 2
to generate the internal pixel clock. PXCK drives the entire
TMC2490A, except the asynchronous microprocessor interface.
All internal registers are strobed on the rising edge of PXCK.
Pixel Data Inputs.
Video data enters the TMC2490A on
PD
7-0
(Figure 1).
Data I/O, General Purpose I/O, Chroma Input Port.
When SER
is HIGH, all control parameters are loaded into and read back
over this 8-bit port. When SER = LOW, D
0
can serve as a
composite sync output, D
1
outputs a burst flag during the back
porch, D
2-5
are General Purpose Outputs, and D
6-7
are General
Purpose Inputs.
Master Reset Input.
Bringing RESET LOW forces the internal
state machines to their starting states and disables all outputs.
Serial/Parallel Port Select.
When SER is LOW, SA
1
in
conjunction with SA
0
selects one of four addresses for the
TMC2490A.
Serial/Parallel Port Select.
When SER is LOW, SA
0
in
conjunction with SA
1
selects one-of-four addresses for the
TMC2490A. When SER is HIGH, this control governs whether the
parallel microprocessor interface selects a table address or
reads/writes table contents.
Pin Number
Value
Pin Function Description
Data Input Port
PD
7-0
38–44, 3
TTL
Microprocessor Interface
D
7-0
9–12, 14–17
TTL
RESET
SA
1
22
4
TTL
TTL
SA
0
, ADR
5
TTL
3
TMC2490A
PRODUCT SPECIFICATION
Pin Descriptions
(continued)
Pin Name
SDA, R/W
Pin Number
6
Value
R-Bus/TTL
Pin Function Description
Serial Data/Read/Write Control.
When SER is LOW, SDA is the
data line of the serial interface. When SER is HIGH, the pin is the
read/write control for the parallel interface. When R/W and CS are
LOW, the microprocessor can write to the control registers over
D
7-0
. When R/W is HIGH and CS is LOW, it can read the
contents of any selected control register over D
7-0
.
Serial Clock/Chip Select.
When SER is LOW, SCL is the clock
line of the serial interface. When SER is HIGH, the pin is the chip
select control for the parallel interface. When CS is HIGH, the
microprocessor interface port, D
7-0
, is set to HIGH impedance
and ignored. When CS is LOW, the microprocessor can read or
write parameters over D
7-0
.
Serial/Parallel Port Select.
When LOW, the 2-line serial
interface is activated. Pins 5, 6, and 7 function as SA
0
, SDA, and
SCL respectively. When HIGH, the parallel interface port is active
and pins 5, 6, and 7 function as ADR, R/W, and CS respectively.
Chrominance-only Video.
Analog output of chrominance D/A
converter. Maximum output is 1.35 volts peak-to-peak into a
doubly terminated 75 Ohm load.
Composite NTSC/PAL Video.
Analog output of composite D/A
converter. Maximum output is 1.35 volts peak-to-peak into a
doubly terminated 75 Ohm load.
Luminance-only Video.
Analog output of luminance D/A
converter. Maximum output is 1.35 volts peak-to-peak into a
doubly terminated 75 Ohm load.
Reference Bypass Capacitor.
Connection point for 0.1
µ
F
decoupling capacitor to V
DD
at pin 34.
Current-setting Resistor.
Connection point for external current-
setting resistor for D/A converters. The resistor is connected
between R
REF
and GND. Output video levels are inversely
proportional to the value of R
REF
.
Voltage Reference Input.
External voltage reference input,
internal voltage reference output, nominally 1.235 V.
Horizontal Sync Output.
Vertical Sync Output or Odd/Even Field ID Output
.
Pixel Data Phase Output or Video Blanking Output.
Luma/Chroma MUX Control.
Power Supply.
Positive power supply.
Ground.
Analog Power Supply.
Positive power supply.
SCL, CS
7
R-Bus/TTL
SER
8
TTL
Outputs
CHROMA
35
1.35V p-p
COMPOSITE
30
1.35V p-p
LUMA
32
1.35V p-p
Analog Interface
C
BYP
R
REF
33
28
0.1
µ
F
787
Ω
V
REF
SYNC Out
HSYNC
VSYNC, T/B
CBSEL, PDC
SELC
Power Supply
V
DD
GND
V
DDA
27
+1.235V
18
19
20
21
1, 23, 26, 37
2, 13, 24, 29,
31, 36
34
TTL
TTL
TTL
TTL
+5V
0.0V
+5V
REV. 1.0.2 2/27/02
4
PRODUCT SPECIFICATION
TMC2490A
Control Registers
The TMC2490A is initialized and controlled by a set of reg-
isters which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
serial interface port. The parallel port, D
7-0
, is governed by
pins CS, R/W, and ADR. The serial port is controlled by
SDA and SCL.
Table 1. Control Register Map
Reg
00
01
02
03
04
04
04
04
04
04
04
05
05
05
05
05
05
05
05
06
06
06
07-
0D
Bit
7-0
7-0
7-0
7-0
7
6
5
4
3
2
1-0
7
6
5
4
3
2
1
0
7-6
5-3
2-0
7-0
Mnemonic
PARTID2
PARTID1
PARTID0
REVID
MASTER
NGSEL
YCDELAY
RAMPEN
YCDIS
COMPDIS
FORMAT
PALN
BURSTF
CHRBW
SYNCDIS
BURDIS
LUMDIS
CHRDIS
PEDEN
Reserved
FIELD
Reserved
Reserved
Function
Reads back 97h
Reads back 24h
Reads back 90h (91h)
Silicon revision #
Master Mode
NTSC Gain Select
Luma to chroma delay
Modulated ramp enable
LUMA, CHROMA disable
COMPOSITE disable
Television standard select
Select PAL-N Subcarrier
Burst flag disable
Chroma bandwidth select
Sync pulse disable
Color burst disable
Luminance disable
Chrominance disable
Pedestal enable
Program LOW
Field ID (Read only)
Program LOW
Program LOW
20
21
22
22
22
22
22
10-
1F
7-0
Reg
0E
0E
0E
0E
0F
0F
0F
0F
0F
Bit
7
6
1
0
7
5
4
3
1-0
Mnemonic
PORT7-6
PORT5-2
BURSTF
CSYNC
PED21
VSEL
CBSEL
VBIEN
HDSEL
Reserved
Function
General purpose Inputs
General purpose Outputs
Burst Flag Output
Composite Sync Output
VBI Pedestal Enable
Vertical Sync Select
CBSEL/PDC Pin Function
VBI Pixel Data Enable
HSYNC Delay
May be left unprogrammed
TMC2490A Identification Registers (Read only)
General Purpose Port Register
Global Control Register
General Control Register
Reserved Registers
Video Output Control Register
Closed-Caption Insertion Registers
7-0
7-0
7
6
5
4
3-0
CCD1
CCD2
CCON
CCRTS
CCPAR
CCFLD
CCLINE
First Byte of CC Data
Second Byte of CC Data
Enable CC Data Packet
Request To Send Data
Auto Parity Generation
CC Field Select
CC Line Select
Field ID Register
Notes:
1. For each register listed above, all bits not specified are
reserved and should be set to logic LOW to ensure proper
operation.
Reserved Registers
REV. 1.0.2 2/27/02
5
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