Features
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12-bit Battery-cell Voltage Measurement
Simultaneous Battery Cells Measurement in Parallel
Cell Temperature Measurement
Charge Balancing Capability
– Parallel Balancing of Cells Possible
Integrated Power Supply for MCU
Undervoltage Detection
Less than 10 µA Standby Current
Low Cell Imbalance Current (< 10 µA)
Hot Plug-in Capable
Interrupt Timer for Cycling MCU Wake-ups
Cost-efficient Solution Due to Cost-optimized 30V CMOS Technology
Reliable Communication between Stacked ICs Due to Level Shifters with Current
Sources and Checksum Monitoring of Data
Daisy-chainable
– Each IC Monitors up to 6 Battery Cells
– 16 ICs (96 Cells) per String
– No Limit on Number of Strings
Package QFN48 7 mm
×
7 mm
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Li-Ion, NiMH
Battery
Measuring,
Charge
Balancing and
Power-supply
Circuit
ATA6870
Preliminary
Applications
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Battery Measurement, Supply and Monitoring IC for Li-ion and NiMH Battery Systems
in Electric (EV) and Hybrid Electrical (HEV) Vehicles
Benefits
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Highest Safety Level for Li-ion Battery Systems in Combination with ATA6871
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Cost Reduction Due to Integrated Measurement Circuit and High Voltage Power-supply
1. Description
The ATA6870 is a measurement and monitoring circuit designed for Li-ion and NiMH
multicell battery stacks in hybrid electrical vehicles.
The ATA6870 monitors the battery-cell voltage and the battery-cell temperature with a
12-bit ADC.
The circuit also provides charge-balancing capability for each battery-cell.
In addition, a linear regulator is integrated to supply a microcontroller or other external
components. Reliable communication between stacked ICs is achieved by level-shift-
ers with current sources. The ATA6870 can be connected to three, four, five or six
battery-cells. Up to 16 circuits (96 cells) can be cascaded in one string. The number of
strings is not limited.
9116B–AUTO–10/09
2. Block Diagram
Figure 2-1.
Block Diagram
To ATA6870
above
VDDHV
MBAT7
PD_N
DISCH6
Cell 6:
Reference
ADC
Cell Balancing
Digital
Level
Shifter
Standby
Control
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
POW_ENA
VDDHVM
AVDD
MBAT6
MBAT2
3.3V
Internal
Voltage Regulator
Digital
Level
Shifter
DVDD
BIASRES
DISCH1
MBAT1
TEMPREF
Cell 1:
Reference
ADC
Cell Balancing
Logic
Internal Biasing
TEMP2
TEMP1
NTC
NTC
TEMPVSS
Test
Cell
Temperature
Measuring
Digital
Level
Shifter
Interchip
and
Microcontroller
Communication
Interface
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
MCU
GND AVSS DVSS
SCANMODE
PWTST
DTST
VDDFUSE
MFIRST
CS_FUSE
ATST
To ATA6870
below
2
ATA6870 [Preliminary]
9116B–AUTO–10/09
ATA6870 [Preliminary]
3. Pin Configuration
Figure 3-1.
Pinning QFN48, 7 mm
×
7 mm
CS_N_OUT
SCK_OUT
MOSI_OUT
CLK_OUT
DISCH6
VDDHV
MBAT6
MBAT7
IRQ_IN
MISO_IN
VDDHVP
37
48
47
46
45
44
43
42
41
40
39
38
DISCH5
MBAT5
DISCH4
MBAT4
DISCH3
MBAT3
DISCH2
MBAT2
DISCH1
MBAT1
IRQ
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PD_N
36
35
34
33
32
VDDHVM
PD_N_OUT
POW_ENA
PWTST
BIASRES
ATA6870
31
30
29
28
27
26
25
TEMPREF
TEMP2
TEMP1
TEMPVSS
AVSS
AVDD
ATST
SCANMODE
Table 3-1.
Pin Description
Pad Name
DISCH5
MBAT5
DISCH4
MBAT4
DISCH3
MBAT3
DISCH2
MBAT2
DISCH1
MBAT1
IRQ
CLK
CS_N
SCK
MOSI
MISO
MFIRST
Function
Heatslug
Output to drive external cell-balancing transistor
Battery cell sensing line
Output to drive external cell-balancing transistor
Battery cell sensing line
Output to drive external cell-balancing transistor
Battery cell sensing line
Output to drive external cell-balancing transistor
Battery cell sensing line
Output to drive external cell-balancing transistor
Battery cell sensing line
Interrupt output for MCU/ATA6870 below
System clock
Chip select input from MCU/ATA6870 below
SPI clock input from MCU/ATA6870 below
Master Out Slave In input from MCU
Master In Slave Out output for MCU
Select Master/Slave
SPI data input
SPI data output
Remark
Pad Number
Exposed Pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VDDFUSE
MFIRST
CS_FUSE
DVDD
MOSI
DVSS
CS_N
MISO
DTST
GND
SCK
3
9116B–AUTO–10/09
Table 3-1.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin Description (Continued)
Pad Name
DTST
SCANMODE
CS_FUSE
VDDFUSE
DVSS
DVDD
GND
ATST
AVDD
AVSS
TEMPVSS
TEMP1
TEMP2
TEMPREF
BIASRES
PWTST
POW_ENA
PD_N_OUT
VDDHVM
VDDHVP
PD_N
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
VDDHV
MBAT7
DISCH6
MBAT6
Function
Test-mode pin
Test-mode pin
Test-mode pin
Test-mode pin
Digital negative supply
Digital positive supply input (3.3V)
Ground
Test-mode pin
3.3V Regulator output
Analog negative supply
Ground for temperature measuring
Temperature measuring input 1
Temperature measuring input 2
Reference voltage for temperature measuring
Internal supply current adjustment
Test - mode pin
Power regulator enable/disable
Power down output
Power regulator output to supply e.g. an external
microcontroller
Power regulator supply voltage
Power down input
Master In Slave Out input from ATA6870 above
Master Out Slave In output for ATA6870 above
SPI clock output for input of ATA6870 above
Chip select output for input of ATA6870 above
System clock output for input of ATA6870 above
Interrupt input from ATA6870 above
Supply voltage
Battery cell sensing line
Output to drive external cell-balancing transistor
Battery cell sensing line
Keep pin open (output)
Keep pin open (output)
Connected to AVDD
Remark
Keep pin open (output)
Connected to VSSA
Connected to VSSA
Connected to VSSA
Pad Number
4
ATA6870 [Preliminary]
9116B–AUTO–10/09
ATA6870 [Preliminary]
4. ATA6870 System Overview
The ATA6870 can be stacked up to 16 times in one string. The communication with MCU is car-
ried out on the lowest level through an SPI bus. The data on the SPI bus is transmitted to the 15
other ATA6870s using the communication interface implemented inside ATA6870.
Figure 4-1.
Battery Management Architecture with One Battery String
ATA6870
ATA6870
ATA6870
ATA6870
MCU
5
9116B–AUTO–10/09
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