700MHz, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
ICS8735-21
Features
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One differential 3.3V LVPECL output pair
One differential feedback output pair
Differential CLK/nCLK input pair
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 25ps (maximum)
Static phase offset: 50ps ± 100ps
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CLK
nCLK
MR
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
V
CC
PLL_SEL
V
CCA
SEL3
V
CCO
Q
nQ
General Description
The ICS8735-21 is a highly versatile 1:1 Differential-
to-3.3V LVPECL clock generator and a member of
HiPerClockS™
the HiPerClockS™family of High Performance Clock
Solutions from IDT. The CLK, nCLK pair can accept
most standard differential input levels. The
ICS8735-21 has a fully integrated PLL and can be configured as
zero delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 700MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
ICS
Pin Assignments
Block Diagram
PLL_SEL
Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
CLK
Pulldown
nCLK
Pullup
0
Q
nQ
1
QFB
nQFB
ICS8735-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
PLL_SEL
SEL3
V
CCA
V
CC
V
EE
PLL
nc
nc
FB_IN
Pulldown
nFB_IN
Pullup
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
32 31 30 29 28 27 26 25
SEL0
SEL1
nc
nc
1
2
24
V
CCO
nc
Q
nQ
QFB
nQFB
nc
V
CCO
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
CLK
nCLK
nc
MR
ICS8735-21
23
32-Lead VFQFN
3
22
5mm x 5mm x 0.925mm
4
21
package body
5
20
K Package
6
19
Top View
7
8
9
V
CC
nc
18
17
10 11 12 13 14 15 16
V
EE
nc
nc
nFB_IN
FB_IN
SEL2
nc
IDT™ / ICS™
3.3V LVPECL ZERO DELAY CLOCK GENERATOR
1
ICS8735AM-21 REV. A JULY 31, 2008
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Name
CLK
nCLK
nFB_IN
FB_IN
Input
Input
Input
Input
Type
Pulldown
Pullup
Pullup
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input.
Inverting differential feedback input to phase detector for regenerating clocks with “zero delay.”
Non-inverted differential feedback input to phase detector for regenerating clocks with
“zero delay.”
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true
output Q to go low and the inverted output nQ to go high. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
PLL select. Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential feedback output pair. LVPECL interface levels.
Negative supply pin.
Core supply pins.
Analog supply pin.
Output supply pin.
MR
SEL0, SEL1,
SEL2, SEL3
PLL_SEL
nQ, Q
nQFB, QFB
V
EE
V
CC
V
CCA
V
CCO
Input
Pulldown
Input
Pulldown
Input
Output
Output
Power
Power
Power
Power
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
IDT™ / ICS™
3.3V LVPECL ZERO DELAY CLOCK GENERATOR
2
ICS8735AM-21 REV. A JULY 31, 2008
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 - 700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
Q/nQ, QFB/nQFB
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
IDT™ / ICS™
3.3V LVPECL ZERO DELAY CLOCK GENERATOR
3
ICS8735AM-21 REV. A JULY 31, 2008
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q/nQ, QFB/nQFB
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
SEL3
0z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IDT™ / ICS™
3.3V LVPECL ZERO DELAY CLOCK GENERATOR
4
ICS8735AM-21 REV. A JULY 31, 2008
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
20 Lead SOIC
32 Lead VFQFN
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
46.2°C/W (0 lfpm)
37.0°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
150
15
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
SEL[0:3], MR
Input High Current
PLL_SEL
SEL[0:3], MR
I
IL
Input Low Current
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
IDT™ / ICS™
3.3V LVPECL ZERO DELAY CLOCK GENERATOR
5
ICS8735AM-21 REV. A JULY 31, 2008
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