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8735AM-21LFT

Description
700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
File Size731KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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8735AM-21LFT Overview

700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

700MHz, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
ICS8735-21
Features
One differential 3.3V LVPECL output pair
One differential feedback output pair
Differential CLK/nCLK input pair
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 25ps (maximum)
Static phase offset: 50ps ± 100ps
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CLK
nCLK
MR
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
V
CC
PLL_SEL
V
CCA
SEL3
V
CCO
Q
nQ
General Description
The ICS8735-21 is a highly versatile 1:1 Differential-
to-3.3V LVPECL clock generator and a member of
HiPerClockS™
the HiPerClockS™family of High Performance Clock
Solutions from IDT. The CLK, nCLK pair can accept
most standard differential input levels. The
ICS8735-21 has a fully integrated PLL and can be configured as
zero delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 700MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
ICS
Pin Assignments
Block Diagram
PLL_SEL
Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
CLK
Pulldown
nCLK
Pullup
0
Q
nQ
1
QFB
nQFB
ICS8735-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
PLL_SEL
SEL3
V
CCA
V
CC
V
EE
PLL
nc
nc
FB_IN
Pulldown
nFB_IN
Pullup
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
32 31 30 29 28 27 26 25
SEL0
SEL1
nc
nc
1
2
24
V
CCO
nc
Q
nQ
QFB
nQFB
nc
V
CCO
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
CLK
nCLK
nc
MR
ICS8735-21
23
32-Lead VFQFN
3
22
5mm x 5mm x 0.925mm
4
21
package body
5
20
K Package
6
19
Top View
7
8
9
V
CC
nc
18
17
10 11 12 13 14 15 16
V
EE
nc
nc
nFB_IN
FB_IN
SEL2
nc
IDT™ / ICS™
3.3V LVPECL ZERO DELAY CLOCK GENERATOR
1
ICS8735AM-21 REV. A JULY 31, 2008

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Description 700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
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