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874001AGI-05LF

Description
874001 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
Categorysemiconductor    logic   
File Size773KB,18 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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874001AGI-05LF Overview

874001 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20

874001AGI-05LF Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3 V
Rated supply voltage3.3 V
Processing package description6.50 × 4.40 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
packaging shapeRectangle
Package SizeSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.6500 mm
terminal coatingMATTE Tin
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
series874001
Enter conditionsDifferential MUX
Logic IC typePhase locked loop clock driver
Number of inverted outputs0.0
Real output number1
Max-Min frequency640 MHz
PCI Express™ Jitter Attenuator
ICS874001I-05
DATA SHEET
General Description
The ICS874001I-05 is a high performance Jitter Attenuator designed
for use in PCI Express™ systems. In some PCI Express systems,
such as those found in desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter
components from the PLL synthesizer and from the system board.
The ICS874001I-05 has a bandwidth of 6MHz with <1dB peaking,
easily meeting PCI Express Gen2 PLL requirements.
The ICS874001I-05 uses IDT’s 3 Generation FemtoClock
PLL technology to achieve the lowest possible phase noise. The
device is packaged in a small 20-pin TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
RD
®
Features
One differential LVDS output pair
One differential clock input
CLK, nCLK supports the following input levels: LVPECL, LVDS,
LVHSTL, SSTL, HCSL
Input frequency range: 98MHz to 128MHz
Output frequency range: 98MHz to 640MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 50ps (maximum)
Full 3.3V operating supply
PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
PLL_SEL
nc
nc
nc
MR
nc
F_SEL1
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
V
DDO
Q
nQ
nc
nc
GND
nCLK
CLK
OE
ICS874001I-05
Block Diagram
PLL_SEL
Pullup
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
0
CLK
Pulldown
nCLK
Pullup
Phase
Detector
VCO
490 - 640MHz
1
Output Divider
0 0 ÷5
0 1 ÷4
1 0 ÷2 (default)
1 1 ÷1
Q
nQ
Internal Feedback
÷5
MR
Pulldown
2
F_SEL[1:0]
Pullup/Pulldown
OE
Pullup
ICS874001AGI-05 REVISION A JANUARY 14, 2011
1
©2011 Integrated Device Technology, Inc.
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