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874005AG-04LF

Description
874005 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Categorysemiconductor    logic   
File Size176KB,14 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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874005AG-04LF Overview

874005 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24

874005AG-04LF Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals24
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage3.46 V
Minimum supply/operating voltage3.14 V
Rated supply voltage3.3 V
Processing package description4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.6500 mm
terminal coatingMATTE TIN
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelCOMMERCIAL
series874005
Enter conditionsDIFFERENTIAL
Logic IC typePLL BASED CLOCK DRIVER
Number of inverted outputs0.0
Real output number5
Max-Min frequency98 MHz
PCI Express™ Jitter Attenuator
874005-04
Data Sheet
G
ENERAL
D
ESCRIPTION
The 874005-04 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In some PCI
Express systems, such as those found in desktop PCs, the PCI
Express clocks are generated from a low bandwidth, high phase noise
PLL frequency synthesizer. In these systems, a jitter attenuator may
be required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The 874005-04 has 2 PLL bandwidth modes: 300kHz and
2MHz. The 300kHz mode will provide maximum jitter attenuation,
but higher PLL tracking skew and spread spectrum modulation
from the motherboard synthesizer may be attenuated. The 2MHz
bandwidth provides the best tracking skew and will pass most
spread profiles. The 874005-04 supports Serdes reference clock
frequencies of 100MHz, 125MHz and 250MHz.
The 874005-04 uses IDT’s 3
rd
Generation FemtoClock
TM
PLL
technology to achive the lowest possible phase noise. The device is
packaged in a 24 Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-in cards.
F
EATURES
Five differential LVDS output pairs
One differential clock input
Supports 100MHz, 125MHz, and 250MHz Serdes reference
clocks
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 320MHz
Input frequency range: 98MHz - 128MHz
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
RMS phase jitter @ 100MHz (1.875MHz – 20MHz):
0.88ps (typical)
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4
3.3V operating supply
Two bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
PLL B
ANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~300kHz (default)
1 = PLL Bandwidth: ~2MHz
B
LOCK
D
IAGRAM
OEA Pullup
F_SELA Pulldown
BW_SEL Pulldown
0 = ~300kHz
1 = ~2MHz
CLK Pulldown
nCLK Pullup
F_SELA
0 ÷5
(default)
1 ÷4
QA0
nQA0
QA1
P
IN
A
SSIGNMENT
nQB2
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
V
DDA
F_SELA
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
QB2
V
DDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
GND
nCLK
CLK
Phase
Detector
VCO
490 - 640MHz
nQA1
QB0
F_SELB
0 ÷2
(default)
1 ÷4
nQB0
QB1
nQB1
QB2
M = ÷5
(fixed)
874005-04
nQB2
F_SELB Pulldown
MR Pulldown
OEB Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
January 26, 2016
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