TMC2246AH5C2 datasheet, PDF - EEWORLD Datasheet

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TMC2246AH5C2: Description10-BIT, DSP-DIGITAL FILTER, PPGA120; Categorysemiconductor The embedded processor and controller; File Size268KB，18 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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TMC2246AH5C2 Overview

10-BIT, DSP-DIGITAL FILTER, PPGA120

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www.fairchildsemi.com

TMC2246A

Image Filter

11 x 10 bit, 60 MHz

Features

60 MHz computation rate

60 MHz data and coefﬁcient input

Four 11 x 10-bit multipliers

Individual data and coefﬁcient inputs

25-Bit accumulator

Fractional and integer two’s complement data formats

Input and output data latches with user-conﬁgurable

enables

• Selectable 16-bit rounded output

• Internal 1/2 LSB rounding

• Available in 120-pin CPGA, PPGA, MPGA, or MQFP

•

Applications

•

Fast pixel interpolation

Fast image manipulation

Image mixing and keying

High-performance FIR ﬁlters

Adaptive digital ﬁlters

One- and two-dimensional image processing

Description

The TMC2246A is a video-speed convolutional array com-

posed of four 11 x 10 bit registered multipliers followed by a

summer and an accumulator. All eight multiplier inputs are

accessible to the user and may be updated every clock cycle

with integer or fractional two’s complement data. A pipe-

lined architecture, fully registered input and output ports,

and asynchronous three-state output enable control simplify

the design of complex systems.

The data or coefﬁcient inputs to the multipliers may be held

over multiple clock cycles, providing storage for mixing and

ﬁltering coefﬁcients. The 25-bit internal accumulator path

allows two bits of cumulative word growth and may be inter-

nally rounded to 16 bits. Output data are updated every clock

cycle, or may be held under user control. All data inputs, out-

puts, and controls are TTL compatible and (except for the

three-state output enable) are registered on the rising edge of

CLK.

The TMC2246A is uniquely suited to performing pixel inter-

polation in image manipulation and ﬁltering applications. As

a companion to the Fairchild Semiconductor TMC2301 and

TMC2302 Image Manipulation Sequencers, the TMC2246A

can execute a bilinear interpolation of an image (4-pixel ker-

nels) at real-time video rates. Larger kernels or other, more

complex, functions can be realized with no loss in performance

by utilizing multiple devices.

With unrestricted access to all data and coefﬁcient input

ports, the TMC2246A offers considerable ﬂexibility in appli-

cations performing digital ﬁltering, adaptive FIR ﬁlters, mix-

ers, and other similar systems requiring high-speed

processing.

Fabricated in a submicron CMOS process, the TMC2246A

operates at a guaranteed clock rate of 60 MHz over the full

temperature and supply voltage ranges. It is pin- and func-

tion-compatible with Fairchild’s TMC2246, while providing

higher speed operation and lower power dissipation. It is

available in a 120 pin Plastic Pin Grid Array (PPGA), 120

pin Ceramic Pin Grid Array (CPGA), 120 lead MQFP to

PPGA (MPGA), and a 120 lead Metric Quad FlatPack

(MQFP).

REV. 1.0.3 9/11/00

Logic Symbol

TMC2246A

Image Filter

9-0

10-0

9-0

10-0

9-0

10-0

9-0

10-0

ENB1-4

ENSEL

ACC

FSEL

15-0

OCEN

OEN

CLK

TMC2246AH5C2 Related Products

	TMC2246AH5C2	TMC2246	TMC2246AH5C1	TMC2246AH5C	TMC2246AG1C2	TMC2246AG1C1	TMC2246AG1C	TMC2246A
Description	10-BIT, DSP-DIGITAL FILTER, PPGA120	10-BIT, DSP-DIGITAL FILTER, PQFP120	10-BIT, DSP-DIGITAL FILTER, PPGA121	10-BIT, DSP-DIGITAL FILTER, PPGA120	10-BIT, DSP-DIGITAL FILTER, PQFP120	10-BIT, DSP-DIGITAL FILTER, PQFP120	10-BIT, DSP-DIGITAL FILTER, PQFP120	10-BIT, DSP-DIGITAL FILTER, PQFP120
Is it Rohs certified?	-	-	incompatible	incompatible	incompatible	incompatible	incompatible	-
Maker	-	-	Fairchild	Fairchild	Fairchild	Fairchild	Fairchild	-
Parts packaging code	-	-	PGA	PGA	PGA	PGA	PGA	-
package instruction	-	-	PGA, PGA120,13X13	PGA, PGA120,13X13	PGA, PGA120,13X13	PGA, PGA120,13X13	PGA, PGA120,13X13	-
Contacts	-	-	120	120	120	120	120	-
Reach Compliance Code	-	-	unknown	unknown	unknown	unknown	unknown	-
ECCN code	-	-	3A991.A.2	3A991.A.2	3A001.A.3	3A991.A.2	3A991.A.2	-
Other features	-	-	11 BIT COEFFICIENT INPUT BUS	11 BIT COEFFICIENT INPUT BUS	11 BIT COEFFICIENT INPUT BUS	11 BIT COEFFICIENT INPUT BUS	11 BIT COEFFICIENT INPUT BUS	-
boundary scan	-	-	NO	NO	NO	NO	NO	-
maximum clock frequency	-	-	40 MHz	30 MHz	60 MHz	40 MHz	30 MHz	-
External data bus width	-	-	10	10	10	10	10	-
JESD-30 code	-	-	S-PPGA-P120	S-PPGA-P120	S-CPGA-P120	S-CPGA-P120	S-CPGA-P120	-
JESD-609 code	-	-	e0	e0	e0	e0	e0	-
length	-	-	34.16 mm	34.16 mm	34.16 mm	34.16 mm	34.16 mm	-
low power mode	-	-	NO	NO	NO	NO	NO	-
Number of terminals	-	-	120	120	120	120	120	-
Maximum operating temperature	-	-	70 °C	70 °C	70 °C	70 °C	70 °C	-
Output data bus width	-	-	16	16	16	16	16	-
Package body material	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	-
encapsulated code	-	-	PGA	PGA	PGA	PGA	PGA	-
Encapsulate equivalent code	-	-	PGA120,13X13	PGA120,13X13	PGA120,13X13	PGA120,13X13	PGA120,13X13	-
Package shape	-	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	-
Package form	-	-	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	-
Peak Reflow Temperature (Celsius)	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
power supply	-	-	5 V	5 V	5 V	5 V	5 V	-
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	-	-	5.46 mm	5.46 mm	5.46 mm	5.46 mm	5.46 mm	-
Maximum slew rate	-	-	120 mA	95 mA	170 mA	120 mA	95 mA	-
Maximum supply voltage	-	-	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	-
Minimum supply voltage	-	-	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	-
Nominal supply voltage	-	-	5 V	5 V	5 V	5 V	5 V	-
surface mount	-	-	NO	NO	NO	NO	NO	-
technology	-	-	CMOS	CMOS	CMOS	CMOS	CMOS	-
Temperature level	-	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-
Terminal surface	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	-	-	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	-
Terminal pitch	-	-	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	-
Terminal location	-	-	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	-
Maximum time at peak reflow temperature	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
width	-	-	34.16 mm	34.16 mm	34.16 mm	34.16 mm	34.16 mm	-
uPs/uCs/peripheral integrated circuit type	-	-	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	-

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